c03b6305d8
In a -no-pie link we optimize R_PLT_PC to R_PC. Currently we resolve a branch relocation to the link-time zero address. However such a choice tends to cause relocation overflow possibility for RISC architectures. * aarch64: GNU ld: rewrite the instruction to a NOP; ld.lld: branch to the next instruction * mips: GNU ld: branch to the start of the text segment (?); ld.lld: branch to zero * ppc32: GNU ld: rewrite the instruction to a NOP; ld.lld: branch to the current instruction * ppc64: GNU ld: rewrite the instruction to a NOP; ld.lld: branch to the current instruction * riscv: GNU ld: branch to the absolute zero address (with instruction rewriting) * i386/x86_64: GNU ld/ld.lld: branch to the link-time zero address I think that resolving to the same location is a good choice. The instruction, if triggered, is clearly an undefined behavior. Resolving to the same location can cause an infinite loop (making the user aware of the issue) while ensuring no overflow. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D103001
87 lines
2.6 KiB
ArmAsm
87 lines
2.6 KiB
ArmAsm
# REQUIRES: riscv
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# RUN: llvm-mc -filetype=obj -triple=riscv64 %s -o %t.o
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# RUN: llvm-readobj -r %t.o | FileCheck --check-prefix=RELOC %s
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# RUN: ld.lld -e absolute %t.o -o %t
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# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck --check-prefixes=CHECK,PC %s
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# RUN: llvm-readelf -x .data %t | FileCheck --check-prefixes=HEX %s
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# RUN: ld.lld -e absolute %t.o -o %t --export-dynamic
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# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck --check-prefixes=CHECK,PLT %s
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# RUN: llvm-readelf -x .data %t | FileCheck --check-prefixes=HEX %s
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.weak target
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.global absolute, relative, branch
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## Absolute relocations are resolved to 0.
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# RELOC: 0x0 R_RISCV_HI20 target 0x1
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# RELOC-NEXT: 0x4 R_RISCV_LO12_I target 0x1
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# CHECK-LABEL: <absolute>:
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# CHECK-NEXT: lui t0, 0
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# CHECK-NEXT: addi t0, t0, 1
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absolute:
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lui t0, %hi(target+1)
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addi t0, t0, %lo(target+1)
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## Currently, PC-relative relocations are resolved to 0.
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# RELOC-NEXT: 0x8 R_RISCV_PCREL_HI20 target 0x0
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# RELOC-NEXT: 0xC R_RISCV_PCREL_LO12_I .Lpcrel_hi0 0x0
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# RELOC-NEXT: 0x10 R_RISCV_PCREL_HI20 target 0x2
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# RELOC-NEXT: 0x14 R_RISCV_PCREL_LO12_S .Lpcrel_hi1 0x0
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## 1048559 should be -0x11.
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# CHECK-LABEL: <relative>:
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# CHECK-NEXT: 11{{...}}: auipc a1, 1048559
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# PC-NEXT: addi a1, a1, -352
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# PLT-NEXT: addi a1, a1, -792
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# CHECK-LABEL: <.Lpcrel_hi1>:
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# CHECK-NEXT: 11{{...}}: auipc t1, 1048559
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# PC-NEXT: sd a2, -358(t1)
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# PLT-NEXT: sd a2, -798(t1)
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relative:
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la a1, target
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sd a2, target+2, t1
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## Branch relocations
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## If .dynsym does not exist, an undefined weak symbol is non-preemptible.
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## Treat them as PC relative relocations.
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# RELOC: 0x18 R_RISCV_CALL target 0x0
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# RELOC-NEXT: 0x20 R_RISCV_JAL target 0x0
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# RELOC-NEXT: 0x24 R_RISCV_BRANCH target 0x0
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# PC-LABEL: <branch>:
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# PC-NEXT: auipc ra, 0
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# PC-NEXT: jalr ra
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# PC-NEXT: [[#%x,ADDR:]]:
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# PC-SAME: j 0x[[#ADDR]]
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# PC-NEXT: [[#%x,ADDR:]]:
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# PC-SAME: beqz zero, 0x[[#ADDR]]
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## If .dynsym exists, an undefined weak symbol is preemptible.
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## We create a PLT entry and redirect the reference to it.
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# PLT-LABEL: <branch>:
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# PLT-NEXT: auipc ra, 0
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# PLT-NEXT: jalr 56(ra)
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# PLT-NEXT: [[#%x,ADDR:]]:
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# PLT-SAME: j 0x[[#ADDR]]
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# PLT-NEXT: [[#%x,ADDR:]]:
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# PLT-SAME: beqz zero, 0x[[#ADDR]]
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branch:
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call target
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jal x0, target
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beq x0, x0, target
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## Absolute relocations are resolved to 0.
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# RELOC: 0x0 R_RISCV_64 target 0x3
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# RELOC-NEXT: 0x8 R_RISCV_32 target 0x4
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# HEX: section '.data':
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# HEX-NEXT: 03000000 00000000 04000000
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.data
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.p2align 3
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.quad target+3
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.long target+4
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# PC-NOT: .plt:
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# PLT: .plt:
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