2edcde00cb
Early revisions of the VR4300 have a hardware bug where two consecutive multiplications can produce an incorrect result in the second multiply. This revision adds the `-mfix4300` flag to llvm (and clang) which, when passed, provides a software fix for this issue. More precise description of the "mulmul" bug: ``` mul.[s,d] fd,fs,ft mul.[s,d] fd,fs,ft or [D]MULT[U] rs,rt ``` When the above sequence is executed by the CPU, if at least one of the source operands of the first mul instruction happens to be `sNaN`, `0` or `Infinity`, then the second mul instruction may produce an incorrect result. This can happen both if the two mul instructions are next to each other and if the first one is in a delay slot and the second is the first instruction of the branch target. Description of the fix: This fix adds a backend pass to llvm which scans for mul instructions in each basic block and inserts a nop whenever the following conditions are met: - The current instruction is a single or double-precision floating-point mul instruction. - The next instruction is either a mul instruction (any kind) or a branch instruction. Differential Revision: https://reviews.llvm.org/D116238
85 lines
2.1 KiB
CMake
85 lines
2.1 KiB
CMake
add_llvm_component_group(Mips HAS_JIT)
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set(LLVM_TARGET_DEFINITIONS Mips.td)
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tablegen(LLVM MipsGenAsmMatcher.inc -gen-asm-matcher)
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tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM MipsGenCallingConv.inc -gen-callingconv)
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tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM MipsGenDisassemblerTables.inc -gen-disassembler)
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tablegen(LLVM MipsGenFastISel.inc -gen-fast-isel)
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tablegen(LLVM MipsGenGlobalISel.inc -gen-global-isel)
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tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter)
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tablegen(LLVM MipsGenMCPseudoLowering.inc -gen-pseudo-lowering)
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tablegen(LLVM MipsGenRegisterBank.inc -gen-register-bank)
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tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM MipsGenSubtargetInfo.inc -gen-subtarget)
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tablegen(LLVM MipsGenExegesis.inc -gen-exegesis)
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add_public_tablegen_target(MipsCommonTableGen)
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add_llvm_target(MipsCodeGen
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Mips16FrameLowering.cpp
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Mips16HardFloat.cpp
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Mips16HardFloatInfo.cpp
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Mips16InstrInfo.cpp
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Mips16ISelDAGToDAG.cpp
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Mips16ISelLowering.cpp
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Mips16RegisterInfo.cpp
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MipsAnalyzeImmediate.cpp
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MipsAsmPrinter.cpp
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MipsCallLowering.cpp
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MipsCCState.cpp
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MipsConstantIslandPass.cpp
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MipsDelaySlotFiller.cpp
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MipsExpandPseudo.cpp
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MipsFastISel.cpp
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MipsInstrInfo.cpp
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MipsInstructionSelector.cpp
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MipsISelDAGToDAG.cpp
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MipsISelLowering.cpp
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MipsFrameLowering.cpp
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MipsLegalizerInfo.cpp
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MipsBranchExpansion.cpp
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MipsMCInstLower.cpp
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MipsMachineFunction.cpp
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MipsModuleISelDAGToDAG.cpp
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MipsOptimizePICCall.cpp
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MipsOs16.cpp
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MipsPreLegalizerCombiner.cpp
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MipsRegisterBankInfo.cpp
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MipsRegisterInfo.cpp
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MipsSEFrameLowering.cpp
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MipsSEInstrInfo.cpp
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MipsSEISelDAGToDAG.cpp
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MipsSEISelLowering.cpp
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MipsSERegisterInfo.cpp
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MipsSubtarget.cpp
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MipsTargetMachine.cpp
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MipsTargetObjectFile.cpp
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MicroMipsSizeReduction.cpp
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MipsMulMulBugPass.cpp
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LINK_COMPONENTS
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Analysis
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AsmPrinter
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CodeGen
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Core
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MC
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MipsDesc
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MipsInfo
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SelectionDAG
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Support
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Target
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GlobalISel
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ADD_TO_COMPONENT
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Mips
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)
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add_subdirectory(AsmParser)
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add_subdirectory(Disassembler)
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add_subdirectory(MCTargetDesc)
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add_subdirectory(TargetInfo)
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