8bde5e58c0
The delayed stack protector feature which is currently used for SDAG (and thus allows for more commonly generating tail calls) depends on being able to extract the tail call into a separate return block. To do this it also has to extract the vreg->physreg copies that set up the call's arguments, since if it doesn't then the call inst ends up using undefined physregs in it's new spliced block. SelectionDAG implementations can do this because they delay emitting register copies until *after* the stack arguments are set up. GISel however just processes and emits the arguments in IR order, so stack arguments always end up last, and thus this breaks the code that looks for any register arg copies that precede the call instruction. This patch adds a thunk argument to the assignValueToReg() and custom assignment hooks. For outgoing arguments, register assignments use this return param to return a thunk that does the actual generating of the copies. We collect these until all the outgoing stack assignments have been done and then execute them, so that the copies (and perhaps some artifacts like G_SEXTs) are placed after any stores. Differential Revision: https://reviews.llvm.org/D110610
73 lines
2.4 KiB
C++
73 lines
2.4 KiB
C++
//===-- PPCCallLowering.h - Call lowering for GlobalISel -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file describes how to lower LLVM calls to machine code calls.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_GISEL_PPCCALLLOWERING_H
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#define LLVM_LIB_TARGET_POWERPC_GISEL_PPCCALLLOWERING_H
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#include "PPCISelLowering.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/IR/CallingConv.h"
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namespace llvm {
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class PPCTargetLowering;
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class PPCCallLowering : public CallLowering {
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public:
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PPCCallLowering(const PPCTargetLowering &TLI);
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bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
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ArrayRef<Register> VRegs, FunctionLoweringInfo &FLI,
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Register SwiftErrorVReg) const override;
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bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
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ArrayRef<ArrayRef<Register>> VRegs,
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FunctionLoweringInfo &FLI) const override;
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bool lowerCall(MachineIRBuilder &MIRBuilder,
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CallLoweringInfo &Info) const override;
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};
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class PPCIncomingValueHandler : public CallLowering::IncomingValueHandler {
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public:
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PPCIncomingValueHandler(MachineIRBuilder &MIRBuilder,
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MachineRegisterInfo &MRI)
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: CallLowering::IncomingValueHandler(MIRBuilder, MRI) {}
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uint64_t StackUsed;
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private:
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void assignValueToReg(Register ValVReg, Register PhysReg,
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CCValAssign VA) override;
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void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
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MachinePointerInfo &MPO, CCValAssign &VA) override;
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Register getStackAddress(uint64_t Size, int64_t Offset,
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MachinePointerInfo &MPO,
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ISD::ArgFlagsTy Flags) override;
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virtual void markPhysRegUsed(unsigned PhysReg) = 0;
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};
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class FormalArgHandler : public PPCIncomingValueHandler {
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void markPhysRegUsed(unsigned PhysReg) override;
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public:
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FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
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: PPCIncomingValueHandler(MIRBuilder, MRI) {}
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};
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} // end namespace llvm
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#endif
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