6f7de819b9
D113805 improved handling of i32 divu/remu on RV64. The basic idea from that can be extended to (mul (and X, C2), C1) where C2 is any mask constant. We can replace the and with an SLLI by shifting by the number of leading zeros in C2 if we also shift C1 left by XLen - lzcnt(C1) bits. This will give the full product XLen additional trailing zeros, putting the result in the output of MULHU. If we can't use ANDI, ZEXT.H, or ZEXT.W, this will avoid materializing C2 in a register. The downside is it make take 1 additional instruction to create C1. But since that's not on the critical path, it can hopefully be interleaved with other operations. The previous tablegen pattern is replaced by custom isel code. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D115310
107 lines
4.8 KiB
TableGen
107 lines
4.8 KiB
TableGen
//===-- RISCVInstrInfoM.td - RISC-V 'M' instructions -------*- tablegen -*-===//
|
|
//
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file describes the RISC-V instructions from the standard 'M', Integer
|
|
// Multiplication and Division instruction set extension.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// RISC-V specific DAG Nodes.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def riscv_mulhsu : SDNode<"RISCVISD::MULHSU", SDTIntBinOp>;
|
|
def riscv_divw : SDNode<"RISCVISD::DIVW", SDT_RISCVIntBinOpW>;
|
|
def riscv_divuw : SDNode<"RISCVISD::DIVUW", SDT_RISCVIntBinOpW>;
|
|
def riscv_remuw : SDNode<"RISCVISD::REMUW", SDT_RISCVIntBinOpW>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let Predicates = [HasStdExtM] in {
|
|
def MUL : ALU_rr<0b0000001, 0b000, "mul">,
|
|
Sched<[WriteIMul, ReadIMul, ReadIMul]>;
|
|
def MULH : ALU_rr<0b0000001, 0b001, "mulh">,
|
|
Sched<[WriteIMul, ReadIMul, ReadIMul]>;
|
|
def MULHSU : ALU_rr<0b0000001, 0b010, "mulhsu">,
|
|
Sched<[WriteIMul, ReadIMul, ReadIMul]>;
|
|
def MULHU : ALU_rr<0b0000001, 0b011, "mulhu">,
|
|
Sched<[WriteIMul, ReadIMul, ReadIMul]>;
|
|
def DIV : ALU_rr<0b0000001, 0b100, "div">,
|
|
Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
|
|
def DIVU : ALU_rr<0b0000001, 0b101, "divu">,
|
|
Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
|
|
def REM : ALU_rr<0b0000001, 0b110, "rem">,
|
|
Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
|
|
def REMU : ALU_rr<0b0000001, 0b111, "remu">,
|
|
Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
|
|
} // Predicates = [HasStdExtM]
|
|
|
|
let Predicates = [HasStdExtM, IsRV64] in {
|
|
def MULW : ALUW_rr<0b0000001, 0b000, "mulw">,
|
|
Sched<[WriteIMul32, ReadIMul32, ReadIMul32]>;
|
|
def DIVW : ALUW_rr<0b0000001, 0b100, "divw">,
|
|
Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>;
|
|
def DIVUW : ALUW_rr<0b0000001, 0b101, "divuw">,
|
|
Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>;
|
|
def REMW : ALUW_rr<0b0000001, 0b110, "remw">,
|
|
Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>;
|
|
def REMUW : ALUW_rr<0b0000001, 0b111, "remuw">,
|
|
Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>;
|
|
} // Predicates = [HasStdExtM, IsRV64]
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Pseudo-instructions and codegen patterns
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let Predicates = [HasStdExtM] in {
|
|
def : PatGprGpr<mul, MUL>;
|
|
def : PatGprGpr<mulhs, MULH>;
|
|
def : PatGprGpr<mulhu, MULHU>;
|
|
def : PatGprGpr<riscv_mulhsu, MULHSU>;
|
|
def : PatGprGpr<sdiv, DIV>;
|
|
def : PatGprGpr<udiv, DIVU>;
|
|
def : PatGprGpr<srem, REM>;
|
|
def : PatGprGpr<urem, REMU>;
|
|
} // Predicates = [HasStdExtM]
|
|
|
|
let Predicates = [HasStdExtM, IsRV64] in {
|
|
// Select W instructions if only the lower 32-bits of the result are used.
|
|
def : PatGprGpr<binop_allwusers<mul>, MULW>;
|
|
|
|
def : PatGprGpr<riscv_divw, DIVW>;
|
|
def : PatGprGpr<riscv_divuw, DIVUW>;
|
|
def : PatGprGpr<riscv_remuw, REMUW>;
|
|
|
|
// Handle the specific cases where using DIVU/REMU would be correct and result
|
|
// in fewer instructions than emitting DIVUW/REMUW then zero-extending the
|
|
// result.
|
|
def : Pat<(and (riscv_divuw (assertzexti32 GPR:$rs1),
|
|
(assertzexti32 GPR:$rs2)), 0xffffffff),
|
|
(DIVU GPR:$rs1, GPR:$rs2)>;
|
|
def : Pat<(and (riscv_remuw (assertzexti32 GPR:$rs1),
|
|
(assertzexti32 GPR:$rs2)), 0xffffffff),
|
|
(REMU GPR:$rs1, GPR:$rs2)>;
|
|
|
|
// Although the sexti32 operands may not have originated from an i32 srem,
|
|
// this pattern is safe as it is impossible for two sign extended inputs to
|
|
// produce a result where res[63:32]=0 and res[31]=1.
|
|
def : Pat<(srem (sexti32 (i64 GPR:$rs1)), (sexti32 (i64 GPR:$rs2))),
|
|
(REMW GPR:$rs1, GPR:$rs2)>;
|
|
} // Predicates = [HasStdExtM, IsRV64]
|
|
|
|
let Predicates = [HasStdExtM, IsRV64, NotHasStdExtZba] in {
|
|
// Special case for calculating the full 64-bit product of a 32x32 unsigned
|
|
// multiply where the inputs aren't known to be zero extended. We can shift the
|
|
// inputs left by 32 and use a MULHU. This saves two SRLIs needed to finish
|
|
// zeroing the upper 32 bits.
|
|
def : Pat<(i64 (mul (and GPR:$rs1, 0xffffffff), (and GPR:$rs2, 0xffffffff))),
|
|
(MULHU (SLLI GPR:$rs1, 32), (SLLI GPR:$rs2, 32))>;
|
|
} // Predicates = [HasStdExtM, IsRV64, NotHasStdExtZba]
|