e7b89c2fc3
The vectoriser sometimes generates predicated vector loops using the llvm.get.active.lane.mask intrinsic so it's important that we are able to calculate a valid cost for the call instruction. When SVE is enabled we are able to use a single whilelo instruction for some vector types - in such cases I've marked the cost as 1. For all other cases I've set the cost according to how the intrinsic will be expanded. Tests added here: Analysis/CostModel/AArch64/sve-intrinsics.ll Analysis/CostModel/ARM/active_lane_mask.ll Analysis/CostModel/RISCV/active_lane_mask.ll Differential Revision: https://reviews.llvm.org/D121109
50 lines
4.1 KiB
LLVM
50 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
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; RUN: opt < %s -passes='print<cost-model>' 2>&1 -disable-output -mtriple=thumbv8m.main-none-eabi | FileCheck %s
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define void @get_lane_mask() {
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; CHECK-LABEL: 'get_lane_mask'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %mask_v16i1_i64 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 undef, i64 undef)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %mask_v8i1_i64 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 undef, i64 undef)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %mask_v4i1_i64 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 undef, i64 undef)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %mask_v2i1_i64 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 undef, i64 undef)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %mask_v16i1_i32 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 undef, i32 undef)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %mask_v8i1_i32 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 undef, i32 undef)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %mask_v4i1_i32 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 undef, i32 undef)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %mask_v2i1_i32 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 undef, i32 undef)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %mask_v16i1_i16 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i16(i16 undef, i16 undef)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %mask_v8i1_i16 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i16(i16 undef, i16 undef)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %mask_v4i1_i16 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i16(i16 undef, i16 undef)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %mask_v2i1_i16 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i16(i16 undef, i16 undef)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
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;
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%mask_v16i1_i64 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 undef, i64 undef)
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%mask_v8i1_i64 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 undef, i64 undef)
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%mask_v4i1_i64 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 undef, i64 undef)
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%mask_v2i1_i64 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 undef, i64 undef)
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%mask_v16i1_i32 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 undef, i32 undef)
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%mask_v8i1_i32 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 undef, i32 undef)
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%mask_v4i1_i32 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 undef, i32 undef)
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%mask_v2i1_i32 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 undef, i32 undef)
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%mask_v16i1_i16 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i16(i16 undef, i16 undef)
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%mask_v8i1_i16 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i16(i16 undef, i16 undef)
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%mask_v4i1_i16 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i16(i16 undef, i16 undef)
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%mask_v2i1_i16 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i16(i16 undef, i16 undef)
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ret void
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}
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declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64, i64)
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declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64, i64)
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declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64, i64)
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declare <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64, i64)
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declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32)
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declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
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declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
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declare <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32, i32)
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declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i16(i16, i16)
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declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i16(i16, i16)
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declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i16(i16, i16)
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declare <2 x i1> @llvm.get.active.lane.mask.v2i1.i16(i16, i16)
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