ca11c480e7
Summary: The change in IRTranslator is not trivial but is NFC as far as I can tell. This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D77292
60 lines
2.6 KiB
LLVM
60 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -mtriple=aarch64 -global-isel %s -o - -stop-after=irtranslator | FileCheck %s
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define i8* @test_simple_alloca(i32 %numelts) {
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; CHECK-LABEL: name: test_simple_alloca
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $w0
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
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; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
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; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
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; CHECK: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]
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; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
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; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
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; CHECK: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s64), 1
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; CHECK: $x0 = COPY [[DYN_STACKALLOC]](p0)
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; CHECK: RET_ReallyLR implicit $x0
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%addr = alloca i8, i32 %numelts
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ret i8* %addr
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}
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define i8* @test_aligned_alloca(i32 %numelts) {
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; CHECK-LABEL: name: test_aligned_alloca
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $w0
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
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; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
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; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
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; CHECK: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]
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; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
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; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
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; CHECK: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s64), 32
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; CHECK: $x0 = COPY [[DYN_STACKALLOC]](p0)
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; CHECK: RET_ReallyLR implicit $x0
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%addr = alloca i8, i32 %numelts, align 32
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ret i8* %addr
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}
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define i128* @test_natural_alloca(i32 %numelts) {
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; CHECK-LABEL: name: test_natural_alloca
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $w0
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
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; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
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; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
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; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
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; CHECK: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]
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; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
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; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
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; CHECK: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s64), 1
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; CHECK: $x0 = COPY [[DYN_STACKALLOC]](p0)
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; CHECK: RET_ReallyLR implicit $x0
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%addr = alloca i128, i32 %numelts
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ret i128* %addr
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}
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