161122ea1c
With the new SVE stack layout, we now need to provide a Darwin variant for all the calling conventions based on the main AAPCS CSR save order. This also changes APCS_SwiftError to have a Darwin and a non-Darwin version, assuming it could be used on other platforms these days, and restricts the AArch64_CXX_TLS calling convention to Darwin. Differential Revision: https://reviews.llvm.org/D73805
26 lines
1.2 KiB
LLVM
26 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -global-isel -mtriple aarch64-apple-ios -stop-after=instruction-select %s -o - | FileCheck %s
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; Check that packing incoming arguments into a big vector type
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; and unpacking them in registers for the call to @bar gets selected as just
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; simple copies. I.e., we don't artificial try to keep the big
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; vector (%vec) alive.
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define void @shuffle_to_concat_vector(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: name: shuffle_to_concat_vector
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $q0 = COPY [[COPY]]
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; CHECK: $q1 = COPY [[COPY1]]
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; CHECK: BL @bar, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $q0, implicit $q1
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: RET_ReallyLR
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%vec = shufflevector <2 x i64> %a, <2 x i64> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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call void @bar(<4 x i64> %vec)
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ret void
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}
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declare void @bar(<4 x i64> %vec)
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