fae05692a3
This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
196 lines
7.0 KiB
YAML
196 lines
7.0 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -verify-machineinstrs -mtriple aarch64--- -run-pass=instruction-select -global-isel %s -o - | FileCheck %s
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---
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name: test_loop_phi_fpr_to_gpr
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alignment: 4
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legalized: true
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regBankSelected: true
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selected: false
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failedISel: false
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tracksRegLiveness: true
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liveins: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: test_loop_phi_fpr_to_gpr
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
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; CHECK: [[DEF1:%[0-9]+]]:gpr64common = IMPLICIT_DEF
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 2143289344
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: [[DEF2:%[0-9]+]]:gpr32 = IMPLICIT_DEF
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; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[DEF]], 0, implicit-def $nzcv
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; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[DEF2]], [[DEF2]], 1, implicit $nzcv
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; CHECK: bb.2:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: [[PHI:%[0-9]+]]:gpr32 = PHI [[CSELWr]], %bb.1, %8, %bb.2
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; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[FCVTHSr]], %subreg.hsub
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; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
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; CHECK: STRHHui [[PHI]], [[DEF1]], 0 :: (store (s16) into `half* undef`)
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; CHECK: B %bb.2
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bb.0:
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successors: %bb.1(0x80000000)
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%0:gpr(s1) = G_IMPLICIT_DEF
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%4:gpr(p0) = G_IMPLICIT_DEF
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%8:fpr(s32) = G_FCONSTANT float 0x7FF8000000000000
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bb.1:
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successors: %bb.2(0x80000000)
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%6:gpr(s32) = G_IMPLICIT_DEF
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%7:gpr(s32) = G_SELECT %0(s1), %6, %6
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%1:gpr(s16) = G_TRUNC %7(s32)
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bb.2:
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successors: %bb.2(0x80000000)
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%3:gpr(s16) = G_PHI %1(s16), %bb.1, %5(s16), %bb.2
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%5:fpr(s16) = G_FPTRUNC %8(s32)
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G_STORE %3(s16), %4(p0) :: (store (s16) into `half* undef`)
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G_BR %bb.2
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...
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---
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name: test_loop_phi_gpr_to_fpr
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alignment: 4
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legalized: true
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regBankSelected: true
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selected: false
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failedISel: false
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tracksRegLiveness: true
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liveins: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: test_loop_phi_gpr_to_fpr
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
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; CHECK: [[DEF1:%[0-9]+]]:gpr64common = IMPLICIT_DEF
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 2143289344
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: [[DEF2:%[0-9]+]]:gpr32 = IMPLICIT_DEF
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; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[DEF]], 0, implicit-def $nzcv
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; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[DEF2]], [[DEF2]], 1, implicit $nzcv
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[CSELWr]]
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; CHECK: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
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; CHECK: bb.2:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: [[PHI:%[0-9]+]]:fpr16 = PHI %7, %bb.2, [[COPY2]], %bb.1
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; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
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; CHECK: STRHui [[PHI]], [[DEF1]], 0 :: (store (s16) into `half* undef`)
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; CHECK: B %bb.2
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bb.0:
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successors: %bb.1(0x80000000)
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%0:gpr(s1) = G_IMPLICIT_DEF
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%4:gpr(p0) = G_IMPLICIT_DEF
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%8:fpr(s32) = G_FCONSTANT float 0x7FF8000000000000
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bb.1:
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successors: %bb.2(0x80000000)
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%6:gpr(s32) = G_IMPLICIT_DEF
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%7:gpr(s32) = G_SELECT %0(s1), %6, %6
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%1:gpr(s16) = G_TRUNC %7(s32)
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bb.2:
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successors: %bb.2(0x80000000)
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%3:fpr(s16) = G_PHI %5(s16), %bb.2, %1(s16), %bb.1
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%5:fpr(s16) = G_FPTRUNC %8(s32)
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G_STORE %3(s16), %4(p0) :: (store (s16) into `half* undef`)
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G_BR %bb.2
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...
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---
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name: multiple_phis
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; The copy we insert in bb.4 should appear after all the phi instructions.
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; CHECK-LABEL: name: multiple_phis
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.5(0x40000000)
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; CHECK: liveins: $w0, $w1, $x2
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; CHECK: %ptr:gpr64sp = COPY $x2
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; CHECK: %cond_1:gpr32 = IMPLICIT_DEF
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; CHECK: %gpr_1:gpr32 = IMPLICIT_DEF
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %gpr_1
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; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub
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; CHECK: TBNZW %cond_1, 0, %bb.5
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; CHECK: B %bb.1
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000)
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; CHECK: %cond_2:gpr32 = IMPLICIT_DEF
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; CHECK: TBNZW %cond_2, 0, %bb.3
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; CHECK: B %bb.2
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; CHECK: bb.2:
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; CHECK: successors: %bb.4(0x80000000)
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; CHECK: %gpr_2:gpr32 = IMPLICIT_DEF
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; CHECK: B %bb.4
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; CHECK: bb.3:
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; CHECK: successors: %bb.4(0x80000000)
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; CHECK: %fpr:fpr16 = IMPLICIT_DEF
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; CHECK: bb.4:
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; CHECK: successors: %bb.5(0x80000000)
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; CHECK: %fp_phi:fpr16 = PHI %fpr, %bb.3, [[COPY1]], %bb.2
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; CHECK: %gp_phi1:gpr32 = PHI %gpr_1, %bb.3, %gpr_2, %bb.2
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; CHECK: %gp_phi2:gpr32 = PHI %gpr_1, %bb.3, %gpr_2, %bb.2
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; CHECK: %gp_phi3:gpr32 = PHI %gpr_1, %bb.3, %gpr_2, %bb.2
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, %fp_phi, %subreg.hsub
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; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
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; CHECK: bb.5:
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; CHECK: %use_fp_phi:gpr32 = PHI %gpr_1, %bb.0, [[COPY2]], %bb.4
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; CHECK: %use_gp_phi1:gpr32 = PHI %gpr_1, %bb.0, %gp_phi1, %bb.4
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; CHECK: %use_gp_phi2:gpr32 = PHI %gpr_1, %bb.0, %gp_phi2, %bb.4
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; CHECK: %use_gp_phi3:gpr32 = PHI %gpr_1, %bb.0, %gp_phi3, %bb.4
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; CHECK: STRHHui %use_fp_phi, %ptr, 0 :: (store (s16))
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; CHECK: STRHHui %use_gp_phi1, %ptr, 0 :: (store (s16))
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; CHECK: STRHHui %use_gp_phi2, %ptr, 0 :: (store (s16))
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; CHECK: STRHHui %use_gp_phi3, %ptr, 0 :: (store (s16))
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; CHECK: RET_ReallyLR
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bb.1:
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successors: %bb.2, %bb.6
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liveins: $w0, $w1, $x2
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%ptr:gpr(p0) = COPY $x2
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%cond_1:gpr(s1) = G_IMPLICIT_DEF
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%gpr_1:gpr(s16) = G_IMPLICIT_DEF
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G_BRCOND %cond_1(s1), %bb.6
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G_BR %bb.2
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bb.2:
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successors: %bb.3, %bb.4
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%cond_2:gpr(s1) = G_IMPLICIT_DEF
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G_BRCOND %cond_2(s1), %bb.4
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G_BR %bb.3
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bb.3:
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%gpr_2:gpr(s16) = G_IMPLICIT_DEF
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G_BR %bb.5
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bb.4:
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%fpr:fpr(s16) = G_IMPLICIT_DEF
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bb.5:
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%fp_phi:fpr(s16) = G_PHI %fpr(s16), %bb.4, %gpr_1(s16), %bb.3
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%gp_phi1:gpr(s16) = G_PHI %gpr_1(s16), %bb.4, %gpr_2(s16), %bb.3
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%gp_phi2:gpr(s16) = G_PHI %gpr_1(s16), %bb.4, %gpr_2(s16), %bb.3
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%gp_phi3:gpr(s16) = G_PHI %gpr_1(s16), %bb.4, %gpr_2(s16), %bb.3
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bb.6:
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%use_fp_phi:gpr(s16) = G_PHI %gpr_1(s16), %bb.1, %fp_phi(s16), %bb.5
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%use_gp_phi1:gpr(s16) = G_PHI %gpr_1(s16), %bb.1, %gp_phi1(s16), %bb.5
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%use_gp_phi2:gpr(s16) = G_PHI %gpr_1(s16), %bb.1, %gp_phi2(s16), %bb.5
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%use_gp_phi3:gpr(s16) = G_PHI %gpr_1(s16), %bb.1, %gp_phi3(s16), %bb.5
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G_STORE %use_fp_phi(s16), %ptr(p0) :: (store (s16))
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G_STORE %use_gp_phi1(s16), %ptr(p0) :: (store (s16))
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G_STORE %use_gp_phi2(s16), %ptr(p0) :: (store (s16))
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G_STORE %use_gp_phi3(s16), %ptr(p0) :: (store (s16))
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RET_ReallyLR
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...
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