e20f69f612
This constrains the Mov* and similar pseudo instruction to take GPR64common register classes rather than GPR64. GPR64 includs XZR which is invalid here, because this pseudo instructions expands into an adrp/add pair sharing a destination register. XZR is invalid on add and attempting to encode it will instead increment the stack pointer causing crashes (downstream report at [1]). The test case there reproduces on LLVM11, but I do not have a test case that reaches this code path on main, since it is being masked by improved dead code elimination introduced in D91513. Nevertheless, this seems like a good thing to fix in case there are other cases that dead code elimination doesn't clean up (e.g. if `optnone` is used and the optimization is skipped). I think it would be worth auditing uses of GPR64 in pseudo instructions to see if there are any similar issues, but I do not have a high enough view of the backend or knowledge of the Aarch64 architecture to do this quickly. [1] https://github.com/JuliaLang/julia/issues/39818 Reviewed By: t.p.northover Differential Revision: https://reviews.llvm.org/D97435
71 lines
2.3 KiB
YAML
71 lines
2.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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@x = external hidden local_unnamed_addr global i32*, align 8
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define void @select_add_low_without_offset() { ret void }
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define void @select_add_low_with_offset() { ret void }
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define void @select_add_low_without_adrp() { ret void }
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...
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---
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name: select_add_low_without_offset
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: select_add_low_without_offset
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; CHECK: liveins: $x0
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; CHECK: %add_low:gpr64common = MOVaddr target-flags(aarch64-page) @x, target-flags(aarch64-pageoff, aarch64-nc) @x
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; CHECK: $x0 = COPY %add_low
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; CHECK: RET_ReallyLR implicit $x0
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%copy:gpr(p0) = COPY $x0
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%adrp:gpr64(p0) = ADRP target-flags(aarch64-page) @x
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%add_low:gpr(p0) = G_ADD_LOW %adrp(p0), target-flags(aarch64-pageoff, aarch64-nc) @x
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$x0 = COPY %add_low
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RET_ReallyLR implicit $x0
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...
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---
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name: select_add_low_with_offset
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: select_add_low_with_offset
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; CHECK: liveins: $x0
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; CHECK: %add_low:gpr64common = MOVaddr target-flags(aarch64-page) @x + 1, target-flags(aarch64-pageoff, aarch64-nc) @x + 1
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; CHECK: $x0 = COPY %add_low
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; CHECK: RET_ReallyLR implicit $x0
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%copy:gpr(p0) = COPY $x0
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%adrp:gpr64(p0) = ADRP target-flags(aarch64-page) @x + 1
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%add_low:gpr(p0) = G_ADD_LOW %adrp(p0), target-flags(aarch64-pageoff, aarch64-nc) @x + 1
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$x0 = COPY %add_low
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RET_ReallyLR implicit $x0
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...
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---
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name: select_add_low_without_adrp
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: select_add_low_without_adrp
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; CHECK: liveins: $x0
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; CHECK: %ptr:gpr64sp = COPY $x0
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; CHECK: %add_low:gpr64sp = ADDXri %ptr, target-flags(aarch64-pageoff, aarch64-nc) @x, 0
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; CHECK: $x0 = COPY %add_low
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; CHECK: RET_ReallyLR implicit $x0
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%ptr:gpr(p0) = COPY $x0
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%add_low:gpr(p0) = G_ADD_LOW %ptr(p0), target-flags(aarch64-pageoff, aarch64-nc) @x
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$x0 = COPY %add_low
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RET_ReallyLR implicit $x0
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