fae05692a3
This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
241 lines
7.6 KiB
YAML
241 lines
7.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -mattr=+lse -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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define void @atomicrmw_xchg_i64(i64* %addr) { ret void }
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define void @atomicrmw_add_i64(i64* %addr) { ret void }
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define void @atomicrmw_add_i32(i64* %addr) { ret void }
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define void @atomicrmw_sub_i32(i64* %addr) { ret void }
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define void @atomicrmw_and_i32(i64* %addr) { ret void }
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; nand isn't legal
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define void @atomicrmw_or_i32(i64* %addr) { ret void }
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define void @atomicrmw_xor_i32(i64* %addr) { ret void }
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define void @atomicrmw_min_i32(i64* %addr) { ret void }
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define void @atomicrmw_max_i32(i64* %addr) { ret void }
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define void @atomicrmw_umin_i32(i64* %addr) { ret void }
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define void @atomicrmw_umax_i32(i64* %addr) { ret void }
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...
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---
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name: atomicrmw_xchg_i64
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: atomicrmw_xchg_i64
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
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; CHECK: [[SWPX:%[0-9]+]]:gpr64 = SWPX [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic (s64) on %ir.addr)
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; CHECK: $x0 = COPY [[SWPX]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 1
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%2:gpr(s64) = G_ATOMICRMW_XCHG %0, %1 :: (load store monotonic (s64) on %ir.addr)
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$x0 = COPY %2(s64)
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...
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---
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name: atomicrmw_add_i64
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: atomicrmw_add_i64
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
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; CHECK: [[LDADDX:%[0-9]+]]:gpr64 = LDADDX [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic (s64) on %ir.addr)
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; CHECK: $x0 = COPY [[LDADDX]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 1
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%2:gpr(s64) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic (s64) on %ir.addr)
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$x0 = COPY %2(s64)
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...
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---
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name: atomicrmw_add_i32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: atomicrmw_add_i32
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[MOVi32imm]], [[COPY]] :: (load store seq_cst (s32) on %ir.addr)
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; CHECK: $w0 = COPY [[LDADDALW]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst (s32) on %ir.addr)
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$w0 = COPY %2(s32)
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...
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---
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name: atomicrmw_sub_i32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: atomicrmw_sub_i32
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[MOVi32imm]], [[COPY]] :: (load store seq_cst (s32) on %ir.addr)
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; CHECK: $w0 = COPY [[LDADDALW]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst (s32) on %ir.addr)
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$w0 = COPY %2(s32)
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...
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---
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name: atomicrmw_and_i32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: atomicrmw_and_i32
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[MOVi32imm]]
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; CHECK: [[LDCLRAW:%[0-9]+]]:gpr32 = LDCLRAW [[ORNWrr]], [[COPY]] :: (load store acquire (s32) on %ir.addr)
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; CHECK: $w0 = COPY [[LDCLRAW]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s32) = G_ATOMICRMW_AND %0, %1 :: (load store acquire (s32) on %ir.addr)
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$w0 = COPY %2(s32)
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...
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---
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name: atomicrmw_or_i32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: atomicrmw_or_i32
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[LDSETLW:%[0-9]+]]:gpr32 = LDSETLW [[MOVi32imm]], [[COPY]] :: (load store release (s32) on %ir.addr)
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; CHECK: $w0 = COPY [[LDSETLW]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s32) = G_ATOMICRMW_OR %0, %1 :: (load store release (s32) on %ir.addr)
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$w0 = COPY %2(s32)
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...
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---
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name: atomicrmw_xor_i32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: atomicrmw_xor_i32
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[LDEORALW:%[0-9]+]]:gpr32 = LDEORALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (s32) on %ir.addr)
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; CHECK: $w0 = COPY [[LDEORALW]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s32) = G_ATOMICRMW_XOR %0, %1 :: (load store acq_rel (s32) on %ir.addr)
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$w0 = COPY %2(s32)
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...
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---
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name: atomicrmw_min_i32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: atomicrmw_min_i32
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[LDSMINALW:%[0-9]+]]:gpr32 = LDSMINALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (s32) on %ir.addr)
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; CHECK: $w0 = COPY [[LDSMINALW]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s32) = G_ATOMICRMW_MIN %0, %1 :: (load store acq_rel (s32) on %ir.addr)
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$w0 = COPY %2(s32)
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...
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---
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name: atomicrmw_max_i32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: atomicrmw_max_i32
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[LDSMAXALW:%[0-9]+]]:gpr32 = LDSMAXALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (s32) on %ir.addr)
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; CHECK: $w0 = COPY [[LDSMAXALW]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s32) = G_ATOMICRMW_MAX %0, %1 :: (load store acq_rel (s32) on %ir.addr)
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$w0 = COPY %2(s32)
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...
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---
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name: atomicrmw_umin_i32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: atomicrmw_umin_i32
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[LDUMINALW:%[0-9]+]]:gpr32 = LDUMINALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (s32) on %ir.addr)
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; CHECK: $w0 = COPY [[LDUMINALW]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s32) = G_ATOMICRMW_UMIN %0, %1 :: (load store acq_rel (s32) on %ir.addr)
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$w0 = COPY %2(s32)
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...
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---
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name: atomicrmw_umax_i32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: atomicrmw_umax_i32
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[LDUMAXALW:%[0-9]+]]:gpr32 = LDUMAXALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (s32) on %ir.addr)
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; CHECK: $w0 = COPY [[LDUMAXALW]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s32) = G_ATOMICRMW_UMAX %0, %1 :: (load store acq_rel (s32) on %ir.addr)
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$w0 = COPY %2(s32)
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...
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