245047dfe8
This patch adds support for vector @llvm.ceil intrinsics when full 16 bit floating point support isn't available. To do this, this patch... - Implements basic isel for G_UNMERGE_VALUES - Teaches the legalizer about 16 bit floats - Teaches AArch64RegisterBankInfo to respect floating point registers on G_BUILD_VECTOR and G_UNMERGE_VALUES - Teaches selectCopy about 16-bit floating point vectors It also adds - A legalizer test for the 16-bit vector ceil which verifies that we create a G_UNMERGE_VALUES and G_BUILD_VECTOR when full fp16 isn't supported - An instruction selection test which makes sure we lower to G_FCEIL when full fp16 is supported - A test for selecting G_UNMERGE_VALUES And also updates arm64-vfloatintrinsics.ll to show that the new ceiling types work as expected. https://reviews.llvm.org/D56682 llvm-svn: 352113
131 lines
2.9 KiB
YAML
131 lines
2.9 KiB
YAML
# RUN: llc -verify-machineinstrs -mtriple aarch64--- \
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# RUN: -run-pass=instruction-select -mattr=+fullfp16 -global-isel %s -o - \
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# RUN: | FileCheck %s
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...
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---
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name: ceil_float
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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; CHECK-LABEL: name: ceil_float
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; CHECK: %{{[0-9]+}}:fpr32 = FRINTPSr %{{[0-9]+}}
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liveins: $s0
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%0:fpr(s32) = COPY $s0
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%1:fpr(s32) = G_FCEIL %0
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$s0 = COPY %1(s32)
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...
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---
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name: ceil_double
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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; CHECK-LABEL: name: ceil_double
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; CHECK: %{{[0-9]+}}:fpr64 = FRINTPDr %{{[0-9]+}}
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liveins: $d0
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%0:fpr(s64) = COPY $d0
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%1:fpr(s64) = G_FCEIL %0
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$d0 = COPY %1(s64)
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...
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---
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name: ceil_v2f32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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; CHECK-LABEL: name: ceil_v2f32
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; CHECK: %{{[0-9]+}}:fpr64 = FRINTPv2f32 %{{[0-9]+}}
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liveins: $d0
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%0:fpr(<2 x s32>) = COPY $d0
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%1:fpr(<2 x s32>) = G_FCEIL %0
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$d0 = COPY %1(<2 x s32>)
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...
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---
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name: ceil_v4f32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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; CHECK-LABEL: name: ceil_v4f32
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; CHECK: %{{[0-9]+}}:fpr128 = FRINTPv4f32 %{{[0-9]+}}
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liveins: $q0
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%0:fpr(<4 x s32>) = COPY $q0
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%1:fpr(<4 x s32>) = G_FCEIL %0
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$q0 = COPY %1(<4 x s32>)
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...
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---
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name: ceil_v2f64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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; CHECK-LABEL: name: ceil_v2f64
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; CHECK: %{{[0-9]+}}:fpr128 = FRINTPv2f64 %{{[0-9]+}}
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liveins: $q0
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%0:fpr(<2 x s64>) = COPY $q0
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%1:fpr(<2 x s64>) = G_FCEIL %0
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$q0 = COPY %1(<2 x s64>)
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...
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---
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name: ceil_v4f16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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; CHECK-LABEL: name: ceil_v4f16
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; CHECK: %{{[0-9]+}}:fpr64 = FRINTPv4f16 %{{[0-9]+}}
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liveins: $d0
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%0:fpr(<4 x s16>) = COPY $d0
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%1:fpr(<4 x s16>) = G_FCEIL %0
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$d0 = COPY %1(<4 x s16>)
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...
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---
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name: ceil_v8f16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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; CHECK-LABEL: name: ceil_v8f16
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; CHECK: %{{[0-9]+}}:fpr128 = FRINTPv8f16 %{{[0-9]+}}
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liveins: $q0
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%0:fpr(<8 x s16>) = COPY $q0
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%1:fpr(<8 x s16>) = G_FCEIL %0
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$q0 = COPY %1(<8 x s16>)
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...
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