48904e9452
Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
189 lines
4.7 KiB
YAML
189 lines
4.7 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select -mattr=+fullfp16 -global-isel %s -o - | FileCheck %s
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...
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---
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name: test_f16.rint
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $h0
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; CHECK-LABEL: name: test_f16.rint
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; CHECK: liveins: $h0
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; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
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; CHECK: [[FRINTXHr:%[0-9]+]]:fpr16 = FRINTXHr [[COPY]]
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; CHECK: $h0 = COPY [[FRINTXHr]]
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; CHECK: RET_ReallyLR implicit $h0
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%0:fpr(s16) = COPY $h0
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%1:fpr(s16) = G_FRINT %0
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$h0 = COPY %1(s16)
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RET_ReallyLR implicit $h0
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...
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---
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name: test_f32.rint
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $s0
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; CHECK-LABEL: name: test_f32.rint
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; CHECK: liveins: $s0
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[FRINTXSr:%[0-9]+]]:fpr32 = FRINTXSr [[COPY]]
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; CHECK: $s0 = COPY [[FRINTXSr]]
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; CHECK: RET_ReallyLR implicit $s0
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%0:fpr(s32) = COPY $s0
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%1:fpr(s32) = G_FRINT %0
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$s0 = COPY %1(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: test_f64.rint
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_f64.rint
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[FRINTXDr:%[0-9]+]]:fpr64 = FRINTXDr [[COPY]]
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; CHECK: $d0 = COPY [[FRINTXDr]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(s64) = COPY $d0
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%1:fpr(s64) = G_FRINT %0
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$d0 = COPY %1(s64)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_v4f32.rint
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v4f32.rint
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[FRINTXv4f32_:%[0-9]+]]:fpr128 = FRINTXv4f32 [[COPY]]
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; CHECK: $q0 = COPY [[FRINTXv4f32_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<4 x s32>) = COPY $q0
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%1:fpr(<4 x s32>) = G_FRINT %0
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$q0 = COPY %1(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v2f64.rint
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v2f64.rint
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[FRINTXv2f64_:%[0-9]+]]:fpr128 = FRINTXv2f64 [[COPY]]
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; CHECK: $q0 = COPY [[FRINTXv2f64_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<2 x s64>) = COPY $q0
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%1:fpr(<2 x s64>) = G_FRINT %0
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$q0 = COPY %1(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v4f16.rint
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_v4f16.rint
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[FRINTXv4f16_:%[0-9]+]]:fpr64 = FRINTXv4f16 [[COPY]]
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; CHECK: $d0 = COPY [[FRINTXv4f16_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<4 x s16>) = COPY $d0
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%1:fpr(<4 x s16>) = G_FRINT %0
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$d0 = COPY %1(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_v8f16.rint
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v8f16.rint
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[FRINTXv8f16_:%[0-9]+]]:fpr128 = FRINTXv8f16 [[COPY]]
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; CHECK: $q0 = COPY [[FRINTXv8f16_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<8 x s16>) = COPY $q0
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%1:fpr(<8 x s16>) = G_FRINT %0
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$q0 = COPY %1(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v2f32.rint
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_v2f32.rint
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[FRINTXv2f32_:%[0-9]+]]:fpr64 = FRINTXv2f32 [[COPY]]
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; CHECK: $d0 = COPY [[FRINTXv2f32_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<2 x s32>) = COPY $d0
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%1:fpr(<2 x s32>) = G_FRINT %0
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$d0 = COPY %1(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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