8a316045ed
To do this while supporting the existing functionality in SelectionDAG of using PGO info, we add the ProfileSummaryInfo and LazyBlockFrequencyInfo analysis dependencies to the instruction selector pass. Then, use the predicate to generate constant pool loads for f32 materialization, if we're targeting optsize/minsize. Differential Revision: https://reviews.llvm.org/D97732
135 lines
3.9 KiB
YAML
135 lines
3.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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define void @imm_s32_gpr() { ret void }
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define void @imm_s64_gpr() { ret void }
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define void @test_f64_cp() { ret void }
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define void @test_f32_cp_optsize() #0 { ret void }
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define void @test_f32_cp_minsize() #1 { ret void }
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attributes #0 = { optsize }
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attributes #1 = { minsize }
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...
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---
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# Check that we select a 32-bit immediate into a MOVi32imm.
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name: imm_s32_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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body: |
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bb.0:
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liveins: $w0, $w1
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; CHECK-LABEL: name: imm_s32_gpr
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm -1234
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; CHECK: $w0 = COPY [[MOVi32imm]]
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%0(s32) = G_CONSTANT i32 -1234
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$w0 = COPY %0(s32)
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...
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---
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# Check that we select a 64-bit immediate into a MOVi64imm.
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name: imm_s64_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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body: |
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bb.0:
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liveins: $w0, $w1
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; CHECK-LABEL: name: imm_s64_gpr
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1234
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
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; CHECK: $x0 = COPY [[SUBREG_TO_REG]]
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%0(s64) = G_CONSTANT i64 1234
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$x0 = COPY %0(s64)
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...
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# 64b FP immediates need to be loaded.
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---
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name: test_f64_cp
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legalized: true
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regBankSelected: true
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liveins:
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- { reg: '$d0' }
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body: |
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bb.1 (%ir-block.0):
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liveins: $d0
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; CHECK-LABEL: name: test_f64_cp
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
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; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
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; CHECK: [[FADDDrr:%[0-9]+]]:fpr64 = FADDDrr [[COPY]], [[LDRDui]]
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; CHECK: $d0 = COPY [[FADDDrr]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(s64) = COPY $d0
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%1:fpr(s64) = G_FCONSTANT double 0x3FEFF7CED916872B
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%2:fpr(s64) = G_FADD %0, %1
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$d0 = COPY %2(s64)
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RET_ReallyLR implicit $d0
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...
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# 32b FP immediates need to be loaded if using optsize.
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---
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name: test_f32_cp_optsize
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legalized: true
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regBankSelected: true
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liveins:
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- { reg: '$s0' }
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body: |
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bb.1 (%ir-block.0):
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liveins: $s0
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; CHECK-LABEL: name: test_f32_cp_optsize
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
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; CHECK: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
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; CHECK: [[FADDSrr:%[0-9]+]]:fpr32 = FADDSrr [[COPY]], [[LDRSui]]
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; CHECK: $s0 = COPY [[FADDSrr]]
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; CHECK: RET_ReallyLR implicit $s0
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%0:fpr(s32) = COPY $s0
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%1:fpr(s32) = G_FCONSTANT float 0x3FDB267DE0000000
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%2:fpr(s32) = G_FADD %0, %1
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$s0 = COPY %2(s32)
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RET_ReallyLR implicit $s0
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...
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# 32b FP immediates need to be loaded if using minsize.
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---
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name: test_f32_cp_minsize
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legalized: true
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regBankSelected: true
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liveins:
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- { reg: '$s0' }
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body: |
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bb.1 (%ir-block.0):
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liveins: $s0
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; CHECK-LABEL: name: test_f32_cp_minsize
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
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; CHECK: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
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; CHECK: [[FADDSrr:%[0-9]+]]:fpr32 = FADDSrr [[COPY]], [[LDRSui]]
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; CHECK: $s0 = COPY [[FADDSrr]]
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; CHECK: RET_ReallyLR implicit $s0
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%0:fpr(s32) = COPY $s0
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%1:fpr(s32) = G_FCONSTANT float 0x3FDB267DE0000000
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%2:fpr(s32) = G_FADD %0, %1
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$s0 = COPY %2(s32)
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RET_ReallyLR implicit $s0
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...
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