8f54ebd51d
Add manual selection code similar to the code in AArch64ISelDAGToDAG, and add `createTuple` helpers similar to the code there as well. This accounted for around 111 fallbacks while building clang for AArch64 with GlobalISel. This also should make it easy to add selection code for other store intrinsics. As a minor cleanup, this uses `createQTuple` in the other place where we use REG_SEQUENCE. Differential Revision: https://reviews.llvm.org/D106332
248 lines
8.0 KiB
YAML
248 lines
8.0 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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...
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---
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name: v8i8_ST2Twov8b
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1, $x0
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; CHECK-LABEL: name: v8i8_ST2Twov8b
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; CHECK: liveins: $d0, $d1, $x0
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; CHECK: %ptr:gpr64sp = COPY $x0
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; CHECK: %src1:fpr64 = COPY $d0
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; CHECK: %src2:fpr64 = COPY $d1
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:dd = REG_SEQUENCE %src1, %subreg.dsub0, %src2, %subreg.dsub1
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; CHECK: ST2Twov8b [[REG_SEQUENCE]], %ptr :: (store (<2 x s64>))
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; CHECK: RET_ReallyLR
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%ptr:gpr(p0) = COPY $x0
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%src1:fpr(<8 x s8>) = COPY $d0
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%src2:fpr(<8 x s8>) = COPY $d1
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<8 x s8>), %src2(<8 x s8>), %ptr(p0) :: (store (<2 x s64>))
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RET_ReallyLR
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...
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---
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name: v16i8_ST2Twov16b
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1, $x0
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; CHECK-LABEL: name: v16i8_ST2Twov16b
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; CHECK: liveins: $q0, $q1, $x0
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; CHECK: %ptr:gpr64sp = COPY $x0
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; CHECK: %src1:fpr128 = COPY $q0
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; CHECK: %src2:fpr128 = COPY $q1
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE %src1, %subreg.qsub0, %src2, %subreg.qsub1
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; CHECK: ST2Twov16b [[REG_SEQUENCE]], %ptr :: (store (<4 x s64>))
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; CHECK: RET_ReallyLR
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%ptr:gpr(p0) = COPY $x0
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%src1:fpr(<16 x s8>) = COPY $q0
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%src2:fpr(<16 x s8>) = COPY $q1
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<16 x s8>), %src2(<16 x s8>), %ptr(p0) :: (store (<4 x s64>))
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RET_ReallyLR
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...
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---
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name: v4i16_ST2Twov4h
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1, $x0
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; CHECK-LABEL: name: v4i16_ST2Twov4h
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; CHECK: liveins: $d0, $d1, $x0
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; CHECK: %ptr:gpr64sp = COPY $x0
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; CHECK: %src1:fpr64 = COPY $d0
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; CHECK: %src2:fpr64 = COPY $d1
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:dd = REG_SEQUENCE %src1, %subreg.dsub0, %src2, %subreg.dsub1
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; CHECK: ST2Twov4h [[REG_SEQUENCE]], %ptr :: (store (<2 x s64>))
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; CHECK: RET_ReallyLR
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%ptr:gpr(p0) = COPY $x0
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%src1:fpr(<4 x s16>) = COPY $d0
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%src2:fpr(<4 x s16>) = COPY $d1
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<4 x s16>), %src2(<4 x s16>), %ptr(p0) :: (store (<2 x s64>))
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RET_ReallyLR
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...
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---
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name: v8i16_ST2Twov8h
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1, $x0
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; CHECK-LABEL: name: v8i16_ST2Twov8h
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; CHECK: liveins: $q0, $q1, $x0
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; CHECK: %ptr:gpr64sp = COPY $x0
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; CHECK: %src1:fpr128 = COPY $q0
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; CHECK: %src2:fpr128 = COPY $q1
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE %src1, %subreg.qsub0, %src2, %subreg.qsub1
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; CHECK: ST2Twov8h [[REG_SEQUENCE]], %ptr :: (store (<4 x s64>))
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; CHECK: RET_ReallyLR
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%ptr:gpr(p0) = COPY $x0
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%src1:fpr(<8 x s16>) = COPY $q0
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%src2:fpr(<8 x s16>) = COPY $q1
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<8 x s16>), %src2(<8 x s16>), %ptr(p0) :: (store (<4 x s64>))
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RET_ReallyLR
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...
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---
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name: v2i32_ST2Twov2s
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1, $x0
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; CHECK-LABEL: name: v2i32_ST2Twov2s
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; CHECK: liveins: $d0, $d1, $x0
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; CHECK: %ptr:gpr64sp = COPY $x0
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; CHECK: %src1:fpr64 = COPY $d0
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; CHECK: %src2:fpr64 = COPY $d1
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:dd = REG_SEQUENCE %src1, %subreg.dsub0, %src2, %subreg.dsub1
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; CHECK: ST2Twov2s [[REG_SEQUENCE]], %ptr :: (store (<2 x s64>))
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; CHECK: RET_ReallyLR
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%ptr:gpr(p0) = COPY $x0
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%src1:fpr(<2 x s32>) = COPY $d0
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%src2:fpr(<2 x s32>) = COPY $d1
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<2 x s32>), %src2(<2 x s32>), %ptr(p0) :: (store (<2 x s64>))
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RET_ReallyLR
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...
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---
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name: v4i32_ST2Twov4s
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1, $x0
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; CHECK-LABEL: name: v4i32_ST2Twov4s
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; CHECK: liveins: $q0, $q1, $x0
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; CHECK: %ptr:gpr64sp = COPY $x0
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; CHECK: %src1:fpr128 = COPY $q0
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; CHECK: %src2:fpr128 = COPY $q1
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE %src1, %subreg.qsub0, %src2, %subreg.qsub1
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; CHECK: ST2Twov4s [[REG_SEQUENCE]], %ptr :: (store (<4 x s64>))
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; CHECK: RET_ReallyLR
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%ptr:gpr(p0) = COPY $x0
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%src1:fpr(<4 x s32>) = COPY $q0
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%src2:fpr(<4 x s32>) = COPY $q1
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<4 x s32>), %src2(<4 x s32>), %ptr(p0) :: (store (<4 x s64>))
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RET_ReallyLR
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...
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---
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name: v2i64_ST2Twov2d_s64_elts
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1, $x0
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; CHECK-LABEL: name: v2i64_ST2Twov2d_s64_elts
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; CHECK: liveins: $q0, $q1, $x0
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; CHECK: %ptr:gpr64sp = COPY $x0
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; CHECK: %src1:fpr128 = COPY $q0
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; CHECK: %src2:fpr128 = COPY $q1
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE %src1, %subreg.qsub0, %src2, %subreg.qsub1
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; CHECK: ST2Twov2d [[REG_SEQUENCE]], %ptr :: (store (<4 x s64>))
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; CHECK: RET_ReallyLR
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%ptr:gpr(p0) = COPY $x0
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%src1:fpr(<2 x s64>) = COPY $q0
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%src2:fpr(<2 x s64>) = COPY $q1
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<2 x s64>), %src2(<2 x s64>), %ptr(p0) :: (store (<4 x s64>))
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RET_ReallyLR
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...
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---
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name: v2i64_ST2Twov2d_s64_p0_elts
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1, $x0
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; CHECK-LABEL: name: v2i64_ST2Twov2d_s64_p0_elts
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; CHECK: liveins: $q0, $q1, $x0
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; CHECK: %ptr:gpr64sp = COPY $x0
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; CHECK: %src1:fpr128 = COPY $q0
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; CHECK: %src2:fpr128 = COPY $q1
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE %src1, %subreg.qsub0, %src2, %subreg.qsub1
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; CHECK: ST2Twov2d [[REG_SEQUENCE]], %ptr :: (store (<4 x s64>))
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; CHECK: RET_ReallyLR
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%ptr:gpr(p0) = COPY $x0
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%src1:fpr(<2 x p0>) = COPY $q0
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%src2:fpr(<2 x p0>) = COPY $q1
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<2 x p0>), %src2(<2 x p0>), %ptr(p0) :: (store (<4 x s64>))
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RET_ReallyLR
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...
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---
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name: v1i64_ST1Twov1d_s64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0, $x1, $x2
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; CHECK-LABEL: name: v1i64_ST1Twov1d_s64
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; CHECK: liveins: $x0, $x1, $x2
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; CHECK: %ptr:gpr64sp = COPY $x0
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; CHECK: %src1:gpr64all = COPY $x0
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; CHECK: %src2:gpr64all = COPY $x1
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:dd = REG_SEQUENCE %src1, %subreg.dsub0, %src2, %subreg.dsub1
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; CHECK: ST1Twov1d [[REG_SEQUENCE]], %ptr :: (store (<2 x s64>))
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; CHECK: RET_ReallyLR
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%ptr:gpr(p0) = COPY $x0
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%src1:gpr(s64) = COPY $x0
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%src2:gpr(s64) = COPY $x1
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(s64), %src2(s64), %ptr(p0) :: (store (<2 x s64>))
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RET_ReallyLR
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...
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---
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name: v1i64_ST1Twov1d_p0
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0, $x1, $x2
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; CHECK-LABEL: name: v1i64_ST1Twov1d_p0
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; CHECK: liveins: $x0, $x1, $x2
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; CHECK: %ptr:gpr64sp = COPY $x0
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; CHECK: %src1:gpr64all = COPY $x0
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; CHECK: %src2:gpr64all = COPY $x1
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:dd = REG_SEQUENCE %src1, %subreg.dsub0, %src2, %subreg.dsub1
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; CHECK: ST1Twov1d [[REG_SEQUENCE]], %ptr :: (store (<2 x s64>))
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; CHECK: RET_ReallyLR
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%ptr:gpr(p0) = COPY $x0
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%src1:gpr(p0) = COPY $x0
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%src2:gpr(p0) = COPY $x1
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(p0), %src2(p0), %ptr(p0) :: (store (<2 x s64>))
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RET_ReallyLR
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...
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