04fb9b729a
When the tablegen patterns fail to select a truncating scalar FPR store, our manual selection code also failed to handle it silently, trying to generate an invalid copy. Fix this by adding support in the manual code to generate a proper subreg copy before selecting a non-truncating store.
116 lines
3.0 KiB
YAML
116 lines
3.0 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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define void @truncating_f32(double %x) {
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%alloca = alloca i32, align 4
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%bitcast = bitcast double %x to i64
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%trunc = trunc i64 %bitcast to i32
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store i32 %trunc, i32* %alloca, align 4
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ret void
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}
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define void @truncating_f16(double %x) {
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%alloca = alloca i16, align 2
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%bitcast = bitcast double %x to i64
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%trunc = trunc i64 %bitcast to i16
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store i16 %trunc, i16* %alloca, align 2
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ret void
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}
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define void @truncating_f8(double %x) {
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%alloca = alloca i8, align 1
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%bitcast = bitcast double %x to i64
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%trunc = trunc i64 %bitcast to i8
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store i8 %trunc, i8* %alloca, align 1
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ret void
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}
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...
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---
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name: truncating_f32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$d0' }
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frameInfo:
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maxAlignment: 4
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stack:
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- { id: 0, name: alloca, size: 4, alignment: 4 }
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machineFunctionInfo: {}
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body: |
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bb.1 (%ir-block.0):
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liveins: $d0
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; CHECK-LABEL: name: truncating_f32
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
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; CHECK: STRSui [[COPY1]], %stack.0.alloca, 0 :: (store (s32) into %ir.alloca)
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; CHECK: RET_ReallyLR
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%0:fpr(s64) = COPY $d0
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%1:gpr(p0) = G_FRAME_INDEX %stack.0.alloca
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G_STORE %0(s64), %1(p0) :: (store (s32) into %ir.alloca)
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RET_ReallyLR
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...
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---
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name: truncating_f16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$d0' }
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frameInfo:
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maxAlignment: 2
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stack:
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- { id: 0, name: alloca, size: 2, alignment: 2 }
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machineFunctionInfo: {}
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body: |
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bb.1 (%ir-block.0):
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liveins: $d0
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; CHECK-LABEL: name: truncating_f16
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub
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; CHECK: STRHui [[COPY1]], %stack.0.alloca, 0 :: (store (s16) into %ir.alloca)
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; CHECK: RET_ReallyLR
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%0:fpr(s64) = COPY $d0
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%1:gpr(p0) = G_FRAME_INDEX %stack.0.alloca
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G_STORE %0(s64), %1(p0) :: (store (s16) into %ir.alloca)
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RET_ReallyLR
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...
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---
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name: truncating_f8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$d0' }
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frameInfo:
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maxAlignment: 1
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stack:
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- { id: 0, name: alloca, size: 1, alignment: 1 }
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machineFunctionInfo: {}
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body: |
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bb.1 (%ir-block.0):
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liveins: $d0
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; CHECK-LABEL: name: truncating_f8
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr8 = COPY [[COPY]].bsub
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; CHECK: STRBui [[COPY1]], %stack.0.alloca, 0 :: (store (s8) into %ir.alloca)
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; CHECK: RET_ReallyLR
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%0:fpr(s64) = COPY $d0
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%1:gpr(p0) = G_FRAME_INDEX %stack.0.alloca
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G_STORE %0(s64), %1(p0) :: (store (s8) into %ir.alloca)
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RET_ReallyLR
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...
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