fae05692a3
This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
123 lines
4.2 KiB
YAML
123 lines
4.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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define void @test_store_i8(i32, i8 %val, i8* %addr) { ret void }
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define void @test_store_i16(i32, i16 %val, i16* %addr) { ret void }
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define void @test_store_i32(i32, i32 %val, i32* %addr) { ret void }
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define void @test_store_i64(i32, i64 %val, i64* %addr) { ret void }
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...
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---
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name: test_store_i8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w0, $w1, $x2
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; CHECK-LABEL: name: test_store_i8
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; CHECK: liveins: $w0, $w1, $x2
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
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; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
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; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32
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; CHECK: early-clobber %5:gpr32 = STXRB [[COPY2]], [[COPY1]] :: (volatile store (s8) into %ir.addr)
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; CHECK: $w0 = COPY %5
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; CHECK: RET_ReallyLR implicit $w0
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%3:gpr(s32) = COPY $w1
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%2:gpr(p0) = COPY $x2
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%6:gpr(s64) = G_CONSTANT i64 255
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%7:gpr(s64) = G_ANYEXT %3(s32)
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%4:gpr(s64) = G_AND %7, %6
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%5:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %4(s64), %2(p0) :: (volatile store (s8) into %ir.addr)
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: test_store_i16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w0, $w1, $x2
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; CHECK-LABEL: name: test_store_i16
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; CHECK: liveins: $w0, $w1, $x2
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
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; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
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; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32
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; CHECK: early-clobber %5:gpr32 = STXRH [[COPY2]], [[COPY1]] :: (volatile store (s16) into %ir.addr)
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; CHECK: $w0 = COPY %5
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; CHECK: RET_ReallyLR implicit $w0
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%3:gpr(s32) = COPY $w1
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%2:gpr(p0) = COPY $x2
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%6:gpr(s64) = G_CONSTANT i64 65535
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%7:gpr(s64) = G_ANYEXT %3(s32)
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%4:gpr(s64) = G_AND %7, %6
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%5:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %4(s64), %2(p0) :: (volatile store (s16) into %ir.addr)
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: test_store_i32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w0, $w1, $x2
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; CHECK-LABEL: name: test_store_i32
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; CHECK: liveins: $w0, $w1, $x2
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
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; CHECK: early-clobber %3:gpr32 = STXRW [[COPY]], [[COPY1]] :: (volatile store (s32) into %ir.addr)
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; CHECK: $w0 = COPY %3
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; CHECK: RET_ReallyLR implicit $w0
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%1:gpr(s32) = COPY $w1
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%2:gpr(p0) = COPY $x2
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%3:gpr(s64) = G_ZEXT %1(s32)
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%4:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %3(s64), %2(p0) :: (volatile store (s32) into %ir.addr)
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$w0 = COPY %4(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: test_store_i64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w0, $x1, $x2
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; CHECK-LABEL: name: test_store_i64
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; CHECK: liveins: $w0, $x1, $x2
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
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; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
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; CHECK: early-clobber %2:gpr32 = STXRX [[COPY]], [[COPY1]] :: (volatile store (s64) into %ir.addr)
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; CHECK: $w0 = COPY %2
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; CHECK: RET_ReallyLR implicit $w0
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%1:gpr(s64) = COPY $x1
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%2:gpr(p0) = COPY $x2
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%3:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %1(s64), %2(p0) :: (volatile store (s64) into %ir.addr)
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$w0 = COPY %3(s32)
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RET_ReallyLR implicit $w0
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...
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