fae05692a3
This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
176 lines
4.9 KiB
YAML
176 lines
4.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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define void @zextload_s32_from_s16(i16 *%addr) { ret void }
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define void @zextload_s32_from_s16_not_combined(i16 *%addr) { ret void }
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define i64 @i32_to_i64(i32* %ptr) {
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%ld = load i32, i32* %ptr, align 4
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%val = zext i32 %ld to i64
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ret i64 %val
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}
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define i64 @i16_to_i64(i16* %ptr) {
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%ld = load i16, i16* %ptr, align 2
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%val = zext i16 %ld to i64
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ret i64 %val
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}
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define i64 @i8_to_i64(i8* %ptr) {
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%ld = load i8, i8* %ptr, align 1
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%val = zext i8 %ld to i64
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ret i64 %val
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}
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define i32 @i8_to_i32(i8* %ptr) {
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%ld = load i8, i8* %ptr, align 1
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%val = zext i8 %ld to i32
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ret i32 %val
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}
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define i32 @i16_to_i32(i16* %ptr) {
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%ld = load i16, i16* %ptr, align 2
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%val = zext i16 %ld to i32
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ret i32 %val
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}
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...
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---
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name: zextload_s32_from_s16
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: zextload_s32_from_s16
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.addr)
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; CHECK: $w0 = COPY [[LDRHHui]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s32) = G_ZEXTLOAD %0 :: (load (s16) from %ir.addr)
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$w0 = COPY %1(s32)
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...
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---
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name: zextload_s32_from_s16_not_combined
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: zextload_s32_from_s16_not_combined
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.addr)
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; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
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; CHECK: $w0 = COPY [[COPY1]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s16) = G_LOAD %0 :: (load (s16) from %ir.addr)
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%2:gpr(s32) = G_ZEXT %1
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$w0 = COPY %2(s32)
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...
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---
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name: i32_to_i64
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legalized: true
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regBankSelected: true
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body: |
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bb.1 (%ir-block.0):
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liveins: $x0
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; CHECK-LABEL: name: i32_to_i64
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (s32) from %ir.ptr)
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRWui]], %subreg.sub_32
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; CHECK: $x0 = COPY [[SUBREG_TO_REG]]
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; CHECK: RET_ReallyLR implicit $x0
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%0:gpr(p0) = COPY $x0
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%2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load (s32) from %ir.ptr)
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$x0 = COPY %2(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: i16_to_i64
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legalized: true
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regBankSelected: true
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body: |
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bb.1 (%ir-block.0):
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liveins: $x0
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; CHECK-LABEL: name: i16_to_i64
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.ptr)
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRHHui]], %subreg.sub_32
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; CHECK: $x0 = COPY [[SUBREG_TO_REG]]
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; CHECK: RET_ReallyLR implicit $x0
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%0:gpr(p0) = COPY $x0
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%2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load (s16) from %ir.ptr)
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$x0 = COPY %2(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: i8_to_i64
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legalized: true
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regBankSelected: true
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body: |
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bb.1 (%ir-block.0):
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liveins: $x0
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; CHECK-LABEL: name: i8_to_i64
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8) from %ir.ptr)
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRBBui]], %subreg.sub_32
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; CHECK: $x0 = COPY [[SUBREG_TO_REG]]
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; CHECK: RET_ReallyLR implicit $x0
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%0:gpr(p0) = COPY $x0
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%2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.ptr)
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$x0 = COPY %2(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: i8_to_i32
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legalized: true
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regBankSelected: true
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body: |
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bb.1 (%ir-block.0):
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liveins: $x0
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; CHECK-LABEL: name: i8_to_i32
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8) from %ir.ptr)
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; CHECK: $w0 = COPY [[LDRBBui]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(p0) = COPY $x0
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%2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.ptr)
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: i16_to_i32
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legalized: true
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regBankSelected: true
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body: |
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bb.1 (%ir-block.0):
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liveins: $x0
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; CHECK-LABEL: name: i16_to_i32
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.ptr)
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; CHECK: $w0 = COPY [[LDRHHui]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(p0) = COPY $x0
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%2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load (s16) from %ir.ptr)
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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