93deac2e2b
Fixes the build issue with D111034, whose goal was to optimize add/sub with long immediates. Optimize ([add|sub] r, imm) -> ([ADD|SUB] ([ADD|SUB] r, #imm0, lsl #12), #imm1), if imm == (imm0<<12)+imm1. and both imm0 and imm1 are non-zero 12-bit unsigned integers. Optimize ([add|sub] r, imm) -> ([SUB|ADD] ([SUB|ADD] r, #imm0, lsl #12), #imm1), if imm == -(imm0<<12)-imm1, and both imm0 and imm1 are non-zero 12-bit unsigned integers. The change which fixed the build issue in D111034 was the use of new virtual registers so that SSA form is maintained until deleting MI. Differential Revision: https://reviews.llvm.org/D117429
64 lines
2.3 KiB
YAML
64 lines
2.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -run-pass=aarch64-mi-peephole-opt -o - -mtriple=aarch64-unknown-linux -verify-machineinstrs %s | FileCheck %s
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# Main intention is to verify machine instructions have valid register classes.
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# Use of UBFM[W|X]ri is used as an arbitrary instruction that requires GPR[32|64]RegClass.
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# If the ADD/SUB optimization generates invalid register classes, this test will fail.
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---
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name: addi
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body: |
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bb.0.entry:
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liveins: $w0
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; CHECK-LABEL: name: addi
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; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
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; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 273, 12
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; CHECK-NEXT: [[ADDWri1:%[0-9]+]]:gpr32common = ADDWri [[ADDWri]], 3549, 0
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; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[ADDWri1]], 28, 31
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; CHECK-NEXT: $w0 = COPY [[UBFMWri]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr32 = COPY $w0
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%1:gpr32 = MOVi32imm 1121757
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%2:gpr32 = ADDWrr %0, %1
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%3:gpr32 = UBFMWri %2, 28, 31
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$w0 = COPY %3
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RET_ReallyLR implicit $w0
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...
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---
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name: addl
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: addl
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; CHECK: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
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; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 273, 12
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; CHECK-NEXT: [[ADDXri1:%[0-9]+]]:gpr64common = ADDXri [[ADDXri]], 3549, 0
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; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[ADDXri1]], 28, 31
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; CHECK-NEXT: $x0 = COPY [[UBFMXri]]
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:gpr64 = COPY $x0
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%1:gpr32 = MOVi32imm 1121757
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%2:gpr64 = SUBREG_TO_REG 0, %1, %subreg.sub_32
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%3:gpr64 = ADDXrr %0, killed %2
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%4:gpr64 = UBFMXri %3, 28, 31
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$x0 = COPY %4
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RET_ReallyLR implicit $x0
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...
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---
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name: addl_negate
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: addl_negate
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; CHECK: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
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; CHECK-NEXT: [[SUBXri:%[0-9]+]]:gpr64sp = SUBXri [[COPY]], 273, 12
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; CHECK-NEXT: [[SUBXri1:%[0-9]+]]:gpr64common = SUBXri [[SUBXri]], 3549, 0
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; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBXri1]], 28, 31
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; CHECK-NEXT: $x0 = COPY [[UBFMXri]]
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:gpr64 = COPY $x0
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%1:gpr64 = MOVi64imm -1121757
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%2:gpr64 = ADDXrr %0, killed %1
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%3:gpr64 = UBFMXri %2, 28, 31
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$x0 = COPY %3
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RET_ReallyLR implicit $x0
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