fdce239ae9
We currently use emitConjunction to create CCMP conjunctions from the conditions of selects, helping turning and/ors into more optimal ccmp sequences that don't need to go through csels. This extends that to also be used whilst lowering brcond, giving more opportunity for better condition generation. Differential Revision: https://reviews.llvm.org/D118650
245 lines
5.8 KiB
LLVM
245 lines
5.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-none-none-eabi -verify-machineinstrs %s -o - | FileCheck %s
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declare void @dummy()
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define i32 @and_eq_ne_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_eq_ne_ult:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w2, w3
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; CHECK-NEXT: ccmp w0, w1, #0, ne
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; CHECK-NEXT: ccmp w4, w5, #0, ne
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; CHECK-NEXT: b.hs .LBB0_2
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; CHECK-NEXT: // %bb.1: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp eq i32 %s0, %s1
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%c1 = icmp ne i32 %s2, %s3
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%a = and i1 %c0, %c1
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%c2 = icmp ult i32 %s4, %s5
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%o = or i1 %a, %c2
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br i1 %o, label %if, label %else
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if:
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store i32 1, i32* %p
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ret i32 1
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else:
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ret i32 0
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}
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define i32 @and_ne_ult_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_ne_ult_ule:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w2, w3
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; CHECK-NEXT: ccmp w0, w1, #4, lo
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; CHECK-NEXT: ccmp w4, w5, #0, eq
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; CHECK-NEXT: b.hi .LBB1_2
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; CHECK-NEXT: // %bb.1: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB1_2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp ne i32 %s0, %s1
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%c1 = icmp ult i32 %s2, %s3
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%a = and i1 %c0, %c1
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%c2 = icmp ule i32 %s4, %s5
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%o = or i1 %a, %c2
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br i1 %o, label %if, label %else
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if:
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store i32 1, i32* %p
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ret i32 1
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else:
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ret i32 0
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}
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define i32 @and_ult_ule_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_ult_ule_ugt:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w2, w3
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; CHECK-NEXT: ccmp w0, w1, #2, ls
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; CHECK-NEXT: ccmp w4, w5, #2, hs
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; CHECK-NEXT: b.ls .LBB2_2
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; CHECK-NEXT: // %bb.1: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB2_2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp ult i32 %s0, %s1
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%c1 = icmp ule i32 %s2, %s3
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%a = and i1 %c0, %c1
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%c2 = icmp ugt i32 %s4, %s5
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%o = or i1 %a, %c2
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br i1 %o, label %if, label %else
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if:
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store i32 1, i32* %p
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ret i32 1
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else:
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ret i32 0
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}
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define i32 @and_ule_ugt_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_ule_ugt_uge:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w2, w3
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; CHECK-NEXT: ccmp w0, w1, #2, hi
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; CHECK-NEXT: ccmp w4, w5, #2, hi
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; CHECK-NEXT: b.lo .LBB3_2
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; CHECK-NEXT: // %bb.1: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB3_2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp ule i32 %s0, %s1
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%c1 = icmp ugt i32 %s2, %s3
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%a = and i1 %c0, %c1
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%c2 = icmp uge i32 %s4, %s5
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%o = or i1 %a, %c2
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br i1 %o, label %if, label %else
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if:
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store i32 1, i32* %p
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ret i32 1
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else:
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ret i32 0
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}
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define i32 @and_ugt_uge_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_ugt_uge_slt:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w2, w3
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; CHECK-NEXT: ccmp w0, w1, #0, hs
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; CHECK-NEXT: ccmp w4, w5, #8, ls
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; CHECK-NEXT: b.ge .LBB4_2
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; CHECK-NEXT: // %bb.1: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB4_2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp ugt i32 %s0, %s1
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%c1 = icmp uge i32 %s2, %s3
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%a = and i1 %c0, %c1
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%c2 = icmp slt i32 %s4, %s5
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%o = or i1 %a, %c2
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br i1 %o, label %if, label %else
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if:
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store i32 1, i32* %p
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ret i32 1
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else:
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ret i32 0
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}
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define i32 @and_uge_slt_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_uge_slt_sle:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w2, w3
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; CHECK-NEXT: ccmp w0, w1, #0, lt
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; CHECK-NEXT: ccmp w4, w5, #4, lo
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; CHECK-NEXT: b.gt .LBB5_2
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; CHECK-NEXT: // %bb.1: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB5_2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp uge i32 %s0, %s1
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%c1 = icmp slt i32 %s2, %s3
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%a = and i1 %c0, %c1
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%c2 = icmp sle i32 %s4, %s5
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%o = or i1 %a, %c2
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br i1 %o, label %if, label %else
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if:
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store i32 1, i32* %p
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ret i32 1
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else:
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ret i32 0
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}
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define i32 @and_slt_sle_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_slt_sle_sgt:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w2, w3
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; CHECK-NEXT: ccmp w0, w1, #0, le
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; CHECK-NEXT: ccmp w4, w5, #0, ge
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; CHECK-NEXT: b.le .LBB6_2
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; CHECK-NEXT: // %bb.1: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB6_2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp slt i32 %s0, %s1
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%c1 = icmp sle i32 %s2, %s3
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%a = and i1 %c0, %c1
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%c2 = icmp sgt i32 %s4, %s5
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%o = or i1 %a, %c2
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br i1 %o, label %if, label %else
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if:
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store i32 1, i32* %p
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ret i32 1
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else:
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ret i32 0
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}
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define i32 @and_sle_sgt_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_sle_sgt_sge:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w2, w3
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; CHECK-NEXT: ccmp w0, w1, #0, gt
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; CHECK-NEXT: ccmp w4, w5, #0, gt
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; CHECK-NEXT: b.lt .LBB7_2
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; CHECK-NEXT: // %bb.1: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB7_2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp sle i32 %s0, %s1
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%c1 = icmp sgt i32 %s2, %s3
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%a = and i1 %c0, %c1
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%c2 = icmp sge i32 %s4, %s5
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%o = or i1 %a, %c2
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br i1 %o, label %if, label %else
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if:
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store i32 1, i32* %p
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ret i32 1
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else:
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ret i32 0
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}
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