8689f5e6e7
This change introduces subtarget features to predicate certain instructions and system registers that are available only on 'A' profile targets. Those features are not present when targeting a generic CPU, which is the default processor. In other words the generic CPU now means the intersection of 'A' and 'R' profiles. To maintain backwards compatibility we enable the features that correspond to -march=armv8-a when the architecture is not explicitly specified on the command line. References: https://developer.arm.com/documentation/ddi0600/latest Differential Revision: https://reviews.llvm.org/D110065
74 lines
2.1 KiB
LLVM
74 lines
2.1 KiB
LLVM
; RUN: llc -mtriple=arm64-eabi -mattr=+crc -o - %s | FileCheck %s
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; RUN: llc -mtriple=arm64-eabi -mattr=+v8r -o - %s | FileCheck %s
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; RUN: llc -mtriple=arm64-eabi -mcpu=cortex-a53 -mattr=+crc -o - %s | FileCheck %s
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define i32 @test_crc32b(i32 %cur, i8 %next) {
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; CHECK-LABEL: test_crc32b:
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; CHECK: crc32b w0, w0, w1
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%bits = zext i8 %next to i32
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%val = call i32 @llvm.aarch64.crc32b(i32 %cur, i32 %bits)
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ret i32 %val
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}
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define i32 @test_crc32h(i32 %cur, i16 %next) {
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; CHECK-LABEL: test_crc32h:
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; CHECK: crc32h w0, w0, w1
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%bits = zext i16 %next to i32
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%val = call i32 @llvm.aarch64.crc32h(i32 %cur, i32 %bits)
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ret i32 %val
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}
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define i32 @test_crc32w(i32 %cur, i32 %next) {
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; CHECK-LABEL: test_crc32w:
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; CHECK: crc32w w0, w0, w1
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%val = call i32 @llvm.aarch64.crc32w(i32 %cur, i32 %next)
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ret i32 %val
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}
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define i32 @test_crc32x(i32 %cur, i64 %next) {
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; CHECK-LABEL: test_crc32x:
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; CHECK: crc32x w0, w0, x1
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%val = call i32 @llvm.aarch64.crc32x(i32 %cur, i64 %next)
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ret i32 %val
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}
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define i32 @test_crc32cb(i32 %cur, i8 %next) {
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; CHECK-LABEL: test_crc32cb:
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; CHECK: crc32cb w0, w0, w1
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%bits = zext i8 %next to i32
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%val = call i32 @llvm.aarch64.crc32cb(i32 %cur, i32 %bits)
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ret i32 %val
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}
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define i32 @test_crc32ch(i32 %cur, i16 %next) {
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; CHECK-LABEL: test_crc32ch:
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; CHECK: crc32ch w0, w0, w1
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%bits = zext i16 %next to i32
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%val = call i32 @llvm.aarch64.crc32ch(i32 %cur, i32 %bits)
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ret i32 %val
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}
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define i32 @test_crc32cw(i32 %cur, i32 %next) {
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; CHECK-LABEL: test_crc32cw:
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; CHECK: crc32cw w0, w0, w1
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%val = call i32 @llvm.aarch64.crc32cw(i32 %cur, i32 %next)
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ret i32 %val
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}
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define i32 @test_crc32cx(i32 %cur, i64 %next) {
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; CHECK-LABEL: test_crc32cx:
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; CHECK: crc32cx w0, w0, x1
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%val = call i32 @llvm.aarch64.crc32cx(i32 %cur, i64 %next)
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ret i32 %val
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}
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declare i32 @llvm.aarch64.crc32b(i32, i32)
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declare i32 @llvm.aarch64.crc32h(i32, i32)
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declare i32 @llvm.aarch64.crc32w(i32, i32)
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declare i32 @llvm.aarch64.crc32x(i32, i64)
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declare i32 @llvm.aarch64.crc32cb(i32, i32)
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declare i32 @llvm.aarch64.crc32ch(i32, i32)
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declare i32 @llvm.aarch64.crc32cw(i32, i32)
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declare i32 @llvm.aarch64.crc32cx(i32, i64)
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