bd07c2e266
This changes the lowering of f32 and f64 COPY from a 128bit vector ORR to a fmov of the appropriate type. At least on some CPU's with 64bit NEON data paths this is expected to be faster, and shouldn't be slower on any CPU that treats fmov as a register rename. Differential Revision: https://reviews.llvm.org/D106365
355 lines
12 KiB
LLVM
355 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,GENERIC
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; RUN: llc < %s -O0 -fast-isel -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,FAST
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; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* \
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; RUN: -mtriple=arm64-eabi -aarch64-neon-syntax=apple \
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; RUN: | FileCheck %s --check-prefixes=GISEL,FALLBACK
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; FALLBACK-NOT: remark{{.*}}G_FPEXT{{.*}}(in function: test_vcvt_f64_f32)
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; FALLBACK-NOT: remark{{.*}}fpext{{.*}}(in function: test_vcvt_f64_f32)
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define <2 x double> @test_vcvt_f64_f32(<2 x float> %x) nounwind readnone ssp {
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; CHECK-LABEL: test_vcvt_f64_f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvtl v0.2d, v0.2s
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; CHECK-NEXT: ret
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;
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; GISEL-LABEL: test_vcvt_f64_f32:
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; GISEL: // %bb.0:
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; GISEL-NEXT: fcvtl v0.2d, v0.2s
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; GISEL-NEXT: ret
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%vcvt1.i = fpext <2 x float> %x to <2 x double>
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ret <2 x double> %vcvt1.i
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}
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; FALLBACK-NOT: remark{{.*}}G_FPEXT{{.*}}(in function: test_vcvt_high_f64_f32)
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; FALLBACK-NOT: remark{{.*}}fpext{{.*}}(in function: test_vcvt_high_f64_f32)
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define <2 x double> @test_vcvt_high_f64_f32(<4 x float> %x) nounwind readnone ssp {
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; CHECK-LABEL: test_vcvt_high_f64_f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvtl2 v0.2d, v0.4s
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; CHECK-NEXT: ret
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;
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; GISEL-LABEL: test_vcvt_high_f64_f32:
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; GISEL: // %bb.0:
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; GISEL-NEXT: fcvtl2 v0.2d, v0.4s
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; GISEL-NEXT: ret
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%cvt_in = shufflevector <4 x float> %x, <4 x float> undef, <2 x i32> <i32 2, i32 3>
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%vcvt1.i = fpext <2 x float> %cvt_in to <2 x double>
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ret <2 x double> %vcvt1.i
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}
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define <2 x double> @test_vcvt_high_v1f64_f32_bitcast(<4 x float> %x) nounwind readnone ssp {
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; CHECK-LABEL: test_vcvt_high_v1f64_f32_bitcast:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvtl2 v0.2d, v0.4s
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; CHECK-NEXT: ret
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;
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; GISEL-LABEL: test_vcvt_high_v1f64_f32_bitcast:
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; GISEL: // %bb.0:
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; GISEL-NEXT: fcvtl2 v0.2d, v0.4s
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; GISEL-NEXT: ret
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%bc1 = bitcast <4 x float> %x to <2 x double>
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%ext = shufflevector <2 x double> %bc1, <2 x double> undef, <1 x i32> <i32 1>
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%bc2 = bitcast <1 x double> %ext to <2 x float>
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%r = fpext <2 x float> %bc2 to <2 x double>
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ret <2 x double> %r
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}
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define <2 x double> @test_vcvt_high_v1i64_f32_bitcast(<2 x i64> %x) nounwind readnone ssp {
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; CHECK-LABEL: test_vcvt_high_v1i64_f32_bitcast:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvtl2 v0.2d, v0.4s
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; CHECK-NEXT: ret
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;
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; GISEL-LABEL: test_vcvt_high_v1i64_f32_bitcast:
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; GISEL: // %bb.0:
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; GISEL-NEXT: fcvtl2 v0.2d, v0.4s
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; GISEL-NEXT: ret
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%ext = shufflevector <2 x i64> %x, <2 x i64> undef, <1 x i32> <i32 1>
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%bc2 = bitcast <1 x i64> %ext to <2 x float>
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%r = fpext <2 x float> %bc2 to <2 x double>
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ret <2 x double> %r
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}
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define <2 x double> @test_vcvt_high_v2i32_f32_bitcast(<4 x i32> %x) nounwind readnone ssp {
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; CHECK-LABEL: test_vcvt_high_v2i32_f32_bitcast:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvtl2 v0.2d, v0.4s
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; CHECK-NEXT: ret
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;
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; GISEL-LABEL: test_vcvt_high_v2i32_f32_bitcast:
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; GISEL: // %bb.0:
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; GISEL-NEXT: fcvtl2 v0.2d, v0.4s
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; GISEL-NEXT: ret
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%ext = shufflevector <4 x i32> %x, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
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%bc2 = bitcast <2 x i32> %ext to <2 x float>
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%r = fpext <2 x float> %bc2 to <2 x double>
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ret <2 x double> %r
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}
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define <2 x double> @test_vcvt_high_v4i16_f32_bitcast(<8 x i16> %x) nounwind readnone ssp {
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; CHECK-LABEL: test_vcvt_high_v4i16_f32_bitcast:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvtl2 v0.2d, v0.4s
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; CHECK-NEXT: ret
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;
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; GISEL-LABEL: test_vcvt_high_v4i16_f32_bitcast:
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; GISEL: // %bb.0:
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; GISEL-NEXT: fcvtl2 v0.2d, v0.4s
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; GISEL-NEXT: ret
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%ext = shufflevector <8 x i16> %x, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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%bc2 = bitcast <4 x i16> %ext to <2 x float>
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%r = fpext <2 x float> %bc2 to <2 x double>
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ret <2 x double> %r
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}
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define <2 x double> @test_vcvt_high_v8i8_f32_bitcast(<16 x i8> %x) nounwind readnone ssp {
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; CHECK-LABEL: test_vcvt_high_v8i8_f32_bitcast:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvtl2 v0.2d, v0.4s
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; CHECK-NEXT: ret
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;
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; GISEL-LABEL: test_vcvt_high_v8i8_f32_bitcast:
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; GISEL: // %bb.0:
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; GISEL-NEXT: fcvtl2 v0.2d, v0.4s
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; GISEL-NEXT: ret
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%ext = shufflevector <16 x i8> %x, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%bc2 = bitcast <8 x i8> %ext to <2 x float>
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%r = fpext <2 x float> %bc2 to <2 x double>
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ret <2 x double> %r
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}
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define <4 x float> @test_vcvt_high_v1i64_f16_bitcast(<2 x i64> %x) nounwind readnone ssp {
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; CHECK-LABEL: test_vcvt_high_v1i64_f16_bitcast:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvtl2 v0.4s, v0.8h
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; CHECK-NEXT: ret
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;
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; GISEL-LABEL: test_vcvt_high_v1i64_f16_bitcast:
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; GISEL: // %bb.0:
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; GISEL-NEXT: fcvtl2 v0.4s, v0.8h
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; GISEL-NEXT: ret
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%ext = shufflevector <2 x i64> %x, <2 x i64> undef, <1 x i32> <i32 1>
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%bc2 = bitcast <1 x i64> %ext to <4 x half>
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%r = fpext <4 x half> %bc2 to <4 x float>
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ret <4 x float> %r
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}
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define <4 x float> @test_vcvt_high_v2i32_f16_bitcast(<4 x i32> %x) nounwind readnone ssp {
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; CHECK-LABEL: test_vcvt_high_v2i32_f16_bitcast:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvtl2 v0.4s, v0.8h
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; CHECK-NEXT: ret
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;
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; GISEL-LABEL: test_vcvt_high_v2i32_f16_bitcast:
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; GISEL: // %bb.0:
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; GISEL-NEXT: fcvtl2 v0.4s, v0.8h
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; GISEL-NEXT: ret
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%ext = shufflevector <4 x i32> %x, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
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%bc2 = bitcast <2 x i32> %ext to <4 x half>
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%r = fpext <4 x half> %bc2 to <4 x float>
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ret <4 x float> %r
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}
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define <4 x float> @test_vcvt_high_v4i16_f16_bitcast(<8 x i16> %x) nounwind readnone ssp {
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; CHECK-LABEL: test_vcvt_high_v4i16_f16_bitcast:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvtl2 v0.4s, v0.8h
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; CHECK-NEXT: ret
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;
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; GISEL-LABEL: test_vcvt_high_v4i16_f16_bitcast:
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; GISEL: // %bb.0:
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; GISEL-NEXT: fcvtl2 v0.4s, v0.8h
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; GISEL-NEXT: ret
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%ext = shufflevector <8 x i16> %x, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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%bc2 = bitcast <4 x i16> %ext to <4 x half>
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%r = fpext <4 x half> %bc2 to <4 x float>
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ret <4 x float> %r
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}
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define <4 x float> @test_vcvt_high_v8i8_f16_bitcast(<16 x i8> %x) nounwind readnone ssp {
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; CHECK-LABEL: test_vcvt_high_v8i8_f16_bitcast:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvtl2 v0.4s, v0.8h
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; CHECK-NEXT: ret
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;
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; GISEL-LABEL: test_vcvt_high_v8i8_f16_bitcast:
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; GISEL: // %bb.0:
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; GISEL-NEXT: fcvtl2 v0.4s, v0.8h
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; GISEL-NEXT: ret
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%ext = shufflevector <16 x i8> %x, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%bc2 = bitcast <8 x i8> %ext to <4 x half>
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%r = fpext <4 x half> %bc2 to <4 x float>
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ret <4 x float> %r
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}
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; FALLBACK-NOT: remark{{.*}}G_FPEXT{{.*}}(in function: test_vcvt_f32_f64)
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; FALLBACK-NOT: remark{{.*}}fpext{{.*}}(in function: test_vcvt_f32_f64)
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define <2 x float> @test_vcvt_f32_f64(<2 x double> %v) nounwind readnone ssp {
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; CHECK-LABEL: test_vcvt_f32_f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvtn v0.2s, v0.2d
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; CHECK-NEXT: ret
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;
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; GISEL-LABEL: test_vcvt_f32_f64:
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; GISEL: // %bb.0:
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; GISEL-NEXT: fcvtn v0.2s, v0.2d
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; GISEL-NEXT: ret
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%vcvt1.i = fptrunc <2 x double> %v to <2 x float>
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ret <2 x float> %vcvt1.i
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}
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define half @test_vcvt_f16_f32(<1 x float> %x) {
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; GENERIC-LABEL: test_vcvt_f16_f32:
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; GENERIC: // %bb.0:
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; GENERIC-NEXT: // kill: def $d0 killed $d0 def $q0
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; GENERIC-NEXT: fcvt h0, s0
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; GENERIC-NEXT: ret
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;
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; FAST-LABEL: test_vcvt_f16_f32:
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; FAST: // %bb.0:
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; FAST-NEXT: fmov d1, d0
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; FAST-NEXT: // implicit-def: $q0
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; FAST-NEXT: fmov d0, d1
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; FAST-NEXT: // kill: def $s0 killed $s0 killed $q0
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; FAST-NEXT: fcvt h0, s0
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; FAST-NEXT: ret
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;
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; GISEL-LABEL: test_vcvt_f16_f32:
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; GISEL: // %bb.0:
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; GISEL-NEXT: fmov x8, d0
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; GISEL-NEXT: fmov s0, w8
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; GISEL-NEXT: fcvt h0, s0
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; GISEL-NEXT: ret
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%tmp = fptrunc <1 x float> %x to <1 x half>
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%elt = extractelement <1 x half> %tmp, i32 0
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ret half %elt
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}
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; FALLBACK-NOT: remark{{.*}}G_FPEXT{{.*}}(in function: test_vcvt_high_f32_f64)
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; FALLBACK-NOT: remark{{.*}}fpext{{.*}}(in function: test_vcvt_high_f32_f64)
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define <4 x float> @test_vcvt_high_f32_f64(<2 x float> %x, <2 x double> %v) nounwind readnone ssp {
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; GENERIC-LABEL: test_vcvt_high_f32_f64:
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; GENERIC: // %bb.0:
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; GENERIC-NEXT: // kill: def $d0 killed $d0 def $q0
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; GENERIC-NEXT: fcvtn2 v0.4s, v1.2d
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; GENERIC-NEXT: ret
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;
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; FAST-LABEL: test_vcvt_high_f32_f64:
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; FAST: // %bb.0:
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; FAST-NEXT: fmov d2, d0
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; FAST-NEXT: // implicit-def: $q0
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; FAST-NEXT: fmov d0, d2
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; FAST-NEXT: fcvtn2 v0.4s, v1.2d
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; FAST-NEXT: ret
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;
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; GISEL-LABEL: test_vcvt_high_f32_f64:
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; GISEL: // %bb.0:
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; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
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; GISEL-NEXT: fcvtn2 v0.4s, v1.2d
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; GISEL-NEXT: ret
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%cvt = fptrunc <2 x double> %v to <2 x float>
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%vcvt2.i = shufflevector <2 x float> %x, <2 x float> %cvt, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x float> %vcvt2.i
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}
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define <2 x float> @test_vcvtx_f32_f64(<2 x double> %v) nounwind readnone ssp {
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; CHECK-LABEL: test_vcvtx_f32_f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvtxn v0.2s, v0.2d
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; CHECK-NEXT: ret
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;
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; GISEL-LABEL: test_vcvtx_f32_f64:
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; GISEL: // %bb.0:
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; GISEL-NEXT: fcvtxn v0.2s, v0.2d
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; GISEL-NEXT: ret
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%vcvtx1.i = tail call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %v) nounwind
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ret <2 x float> %vcvtx1.i
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}
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define <4 x float> @test_vcvtx_high_f32_f64(<2 x float> %x, <2 x double> %v) nounwind readnone ssp {
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; GENERIC-LABEL: test_vcvtx_high_f32_f64:
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; GENERIC: // %bb.0:
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; GENERIC-NEXT: // kill: def $d0 killed $d0 def $q0
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; GENERIC-NEXT: fcvtxn2 v0.4s, v1.2d
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; GENERIC-NEXT: ret
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;
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; FAST-LABEL: test_vcvtx_high_f32_f64:
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; FAST: // %bb.0:
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; FAST-NEXT: fmov d2, d0
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; FAST-NEXT: // implicit-def: $q0
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; FAST-NEXT: fmov d0, d2
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; FAST-NEXT: fcvtxn2 v0.4s, v1.2d
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; FAST-NEXT: ret
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;
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; GISEL-LABEL: test_vcvtx_high_f32_f64:
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; GISEL: // %bb.0:
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; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
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; GISEL-NEXT: fcvtxn2 v0.4s, v1.2d
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; GISEL-NEXT: ret
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%vcvtx2.i = tail call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %v) nounwind
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%res = shufflevector <2 x float> %x, <2 x float> %vcvtx2.i, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x float> %res
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}
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declare <2 x double> @llvm.aarch64.neon.vcvthighfp2df(<4 x float>) nounwind readnone
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declare <2 x double> @llvm.aarch64.neon.vcvtfp2df(<2 x float>) nounwind readnone
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declare <2 x float> @llvm.aarch64.neon.vcvtdf2fp(<2 x double>) nounwind readnone
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declare <4 x float> @llvm.aarch64.neon.vcvthighdf2fp(<2 x float>, <2 x double>) nounwind readnone
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declare <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double>) nounwind readnone
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define i16 @to_half(float %in) {
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; GENERIC-LABEL: to_half:
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; GENERIC: // %bb.0:
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; GENERIC-NEXT: fcvt h0, s0
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; GENERIC-NEXT: fmov w0, s0
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; GENERIC-NEXT: ret
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;
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; FAST-LABEL: to_half:
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; FAST: // %bb.0:
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; FAST-NEXT: fcvt h1, s0
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; FAST-NEXT: // implicit-def: $w0
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; FAST-NEXT: fmov s0, w0
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; FAST-NEXT: fmov s0, s1
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; FAST-NEXT: fmov w0, s0
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; FAST-NEXT: // kill: def $w1 killed $w0
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; FAST-NEXT: ret
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;
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; GISEL-LABEL: to_half:
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; GISEL: // %bb.0:
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; GISEL-NEXT: fcvt h0, s0
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; GISEL-NEXT: fmov w0, s0
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; GISEL-NEXT: ret
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%res = call i16 @llvm.convert.to.fp16.f32(float %in)
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ret i16 %res
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}
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define float @from_half(i16 %in) {
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; GENERIC-LABEL: from_half:
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; GENERIC: // %bb.0:
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; GENERIC-NEXT: fmov s0, w0
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; GENERIC-NEXT: fcvt s0, h0
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; GENERIC-NEXT: ret
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;
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; FAST-LABEL: from_half:
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; FAST: // %bb.0:
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; FAST-NEXT: fmov s0, w0
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; FAST-NEXT: // kill: def $h0 killed $h0 killed $s0
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; FAST-NEXT: fcvt s0, h0
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; FAST-NEXT: ret
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;
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; GISEL-LABEL: from_half:
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; GISEL: // %bb.0:
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; GISEL-NEXT: fmov s0, w0
|
|
; GISEL-NEXT: fcvt s0, h0
|
|
; GISEL-NEXT: ret
|
|
%res = call float @llvm.convert.from.fp16.f32(i16 %in)
|
|
ret float %res
|
|
}
|
|
|
|
declare float @llvm.convert.from.fp16.f32(i16) #1
|
|
declare i16 @llvm.convert.to.fp16.f32(float) #1
|