adec922361
We would like to start pushing -mcpu=generic towards enabling the set of
features that improves performance for some CPUs, without hurting any
others. A blend of the performance options hopefully beneficial to all
CPUs. The largest part of that is enabling in-order scheduling using the
Cortex-A55 schedule model. This is similar to the Arm backend change
from eecb353d0e which made -mcpu=generic perform in-order scheduling
using the cortex-a8 schedule model.
The idea is that in-order cpu's require the most help in instruction
scheduling, whereas out-of-order cpus can for the most part out-of-order
schedule around different codegen. Our benchmarking suggests that
hypothesis holds. When running on an in-order core this improved
performance by 3.8% geomean on a set of DSP workloads, 2% geomean on
some other embedded benchmark and between 1% and 1.8% on a set of
singlecore and multicore workloads, all running on a Cortex-A55 cluster.
On an out-of-order cpu the results are a lot more noisy but show flat
performance or an improvement. On the set of DSP and embedded
benchmarks, run on a Cortex-A78 there was a very noisy 1% speed
improvement. Using the most detailed results I could find, SPEC2006 runs
on a Neoverse N1 show a small increase in instruction count (+0.127%),
but a decrease in cycle counts (-0.155%, on average). The instruction
count is very low noise, the cycle count is more noisy with a 0.15%
decrease not being significant. SPEC2k17 shows a small decrease (-0.2%)
in instruction count leading to a -0.296% decrease in cycle count. These
results are within noise margins but tend to show a small improvement in
general.
When specifying an Apple target, clang will set "-target-cpu apple-a7"
on the command line, so should not be affected by this change when
running from clang. This also doesn't enable more runtime unrolling like
-mcpu=cortex-a55 does, only changing the schedule used.
A lot of existing tests have updated. This is a summary of the important
differences:
- Most changes are the same instructions in a different order.
- Sometimes this leads to very minor inefficiencies, such as requiring
an extra mov to move variables into r0/v0 for the return value of a test
function.
- misched-fusion.ll was no longer fusing the pairs of instructions it
should, as per D110561. I've changed the schedule used in the test
for now.
- neon-mla-mls.ll now uses "mul; sub" as opposed to "neg; mla" due to
the different latencies. This seems fine to me.
- Some SVE tests do not always remove movprfx where they did before due
to different register allocation giving different destructive forms.
- The tests argument-blocks-array-of-struct.ll and arm64-windows-calls.ll
produce two LDR where they previously produced an LDP due to
store-pair-suppress kicking in.
- arm64-ldp.ll and arm64-neon-copy.ll are missing pre/postinc on LPD.
- Some tests such as arm64-neon-mul-div.ll and
ragreedy-local-interval-cost.ll have more, less or just different
spilling.
- In aarch64_generated_funcs.ll.generated.expected one part of the
function is no longer outlined. Interestingly if I switch this to use
any other scheduled even less is outlined.
Some of these are expected to happen, such as differences in outlining
or register spilling. There will be places where these result in worse
codegen, places where they are better, with the SPEC instruction counts
suggesting it is not a decrease overall, on average.
Differential Revision: https://reviews.llvm.org/D110830
179 lines
6.0 KiB
LLVM
179 lines
6.0 KiB
LLVM
; FIXME: Add tests for global-isel/fast-isel.
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; RUN: llc < %s -mtriple=arm64-windows | FileCheck %s
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; Returns <= 8 bytes should be in X0.
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%struct.S1 = type { i32, i32 }
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define dso_local i64 @"?f1"() {
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entry:
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; CHECK-LABEL: f1
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; CHECK-DAG: str xzr, [sp, #8]
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; CHECK-DAG: mov x0, xzr
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%retval = alloca %struct.S1, align 4
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%a = getelementptr inbounds %struct.S1, %struct.S1* %retval, i32 0, i32 0
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store i32 0, i32* %a, align 4
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%b = getelementptr inbounds %struct.S1, %struct.S1* %retval, i32 0, i32 1
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store i32 0, i32* %b, align 4
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%0 = bitcast %struct.S1* %retval to i64*
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%1 = load i64, i64* %0, align 4
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ret i64 %1
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}
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; Returns <= 16 bytes should be in X0/X1.
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%struct.S2 = type { i32, i32, i32, i32 }
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define dso_local [2 x i64] @"?f2"() {
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entry:
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; FIXME: Missed optimization, the entire SP push/pop could be removed
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; CHECK-LABEL: f2
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; CHECK: sub sp, sp, #16
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; CHECK-NEXT: .seh_stackalloc 16
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; CHECK-NEXT: .seh_endprologue
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; CHECK-DAG: stp xzr, xzr, [sp]
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; CHECK-DAG: mov x0, xzr
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; CHECK-DAG: mov x1, xzr
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; CHECK: .seh_startepilogue
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; CHECK-NEXT: add sp, sp, #16
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%retval = alloca %struct.S2, align 4
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%a = getelementptr inbounds %struct.S2, %struct.S2* %retval, i32 0, i32 0
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store i32 0, i32* %a, align 4
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%b = getelementptr inbounds %struct.S2, %struct.S2* %retval, i32 0, i32 1
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store i32 0, i32* %b, align 4
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%c = getelementptr inbounds %struct.S2, %struct.S2* %retval, i32 0, i32 2
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store i32 0, i32* %c, align 4
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%d = getelementptr inbounds %struct.S2, %struct.S2* %retval, i32 0, i32 3
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store i32 0, i32* %d, align 4
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%0 = bitcast %struct.S2* %retval to [2 x i64]*
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%1 = load [2 x i64], [2 x i64]* %0, align 4
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ret [2 x i64] %1
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}
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; Arguments > 16 bytes should be passed in X8.
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%struct.S3 = type { i32, i32, i32, i32, i32 }
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define dso_local void @"?f3"(%struct.S3* noalias sret(%struct.S3) %agg.result) {
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entry:
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; CHECK-LABEL: f3
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; CHECK: stp xzr, xzr, [x8]
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; CHECK: str wzr, [x8, #16]
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%a = getelementptr inbounds %struct.S3, %struct.S3* %agg.result, i32 0, i32 0
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store i32 0, i32* %a, align 4
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%b = getelementptr inbounds %struct.S3, %struct.S3* %agg.result, i32 0, i32 1
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store i32 0, i32* %b, align 4
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%c = getelementptr inbounds %struct.S3, %struct.S3* %agg.result, i32 0, i32 2
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store i32 0, i32* %c, align 4
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%d = getelementptr inbounds %struct.S3, %struct.S3* %agg.result, i32 0, i32 3
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store i32 0, i32* %d, align 4
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%e = getelementptr inbounds %struct.S3, %struct.S3* %agg.result, i32 0, i32 4
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store i32 0, i32* %e, align 4
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ret void
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}
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; InReg arguments to non-instance methods must be passed in X0 and returns in
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; X0.
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%class.B = type { i32 }
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define dso_local void @"?f4"(%class.B* inreg noalias nocapture sret(%class.B) %agg.result) {
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entry:
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; CHECK-LABEL: f4
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; CHECK: mov w8, #1
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; CHECK: str w8, [x0]
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%X.i = getelementptr inbounds %class.B, %class.B* %agg.result, i64 0, i32 0
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store i32 1, i32* %X.i, align 4
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ret void
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}
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; InReg arguments to instance methods must be passed in X1 and returns in X0.
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%class.C = type { i8 }
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%class.A = type { i8 }
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define dso_local void @"?inst@C"(%class.C* %this, %class.A* inreg noalias sret(%class.A) %agg.result) {
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entry:
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; CHECK-LABEL: inst@C
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; CHECK-DAG: mov x0, x1
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; CHECK-DAG: str x8, [sp, #8]
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%this.addr = alloca %class.C*, align 8
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store %class.C* %this, %class.C** %this.addr, align 8
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%this1 = load %class.C*, %class.C** %this.addr, align 8
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ret void
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}
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; The following tests correspond to tests in
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; clang/test/CodeGenCXX/microsoft-abi-sret-and-byval.cpp
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; Pod is a trivial HFA
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%struct.Pod = type { [2 x double] }
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; Not an aggregate according to C++14 spec => not HFA according to MSVC
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%struct.NotCXX14Aggregate = type { %struct.Pod }
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; NotPod is a C++14 aggregate. But not HFA, because it contains
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; NotCXX14Aggregate (which itself is not HFA because it's not a C++14
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; aggregate).
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%struct.NotPod = type { %struct.NotCXX14Aggregate }
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; CHECK-LABEL: copy_pod:
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define dso_local %struct.Pod @copy_pod(%struct.Pod* %x) {
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%x1 = load %struct.Pod, %struct.Pod* %x, align 8
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ret %struct.Pod %x1
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; CHECK: ldp d0, d1, [x0]
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}
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i64, i1 immarg)
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; CHECK-LABEL: copy_notcxx14aggregate:
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define dso_local void
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@copy_notcxx14aggregate(%struct.NotCXX14Aggregate* inreg noalias sret(%struct.NotCXX14Aggregate) align 8 %agg.result,
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%struct.NotCXX14Aggregate* %x) {
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%1 = bitcast %struct.NotCXX14Aggregate* %agg.result to i8*
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%2 = bitcast %struct.NotCXX14Aggregate* %x to i8*
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %1, i8* align 8 %2, i64 16, i1 false)
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ret void
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; CHECK: str q0, [x0]
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}
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; CHECK-LABEL: copy_notpod:
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define dso_local [2 x i64] @copy_notpod(%struct.NotPod* %x) {
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%x1 = bitcast %struct.NotPod* %x to [2 x i64]*
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%x2 = load [2 x i64], [2 x i64]* %x1
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ret [2 x i64] %x2
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; CHECK: ldp x8, x1, [x0]
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; CHECK: mov x0, x8
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}
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@Pod = external global %struct.Pod
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; CHECK-LABEL: call_copy_pod:
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define void @call_copy_pod() {
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%x = call %struct.Pod @copy_pod(%struct.Pod* @Pod)
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store %struct.Pod %x, %struct.Pod* @Pod
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ret void
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; CHECK: bl copy_pod
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; CHECK-NEXT: str d0, [{{.*}}]
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; CHECK-NEXT: str d1, [{{.*}}]
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}
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@NotCXX14Aggregate = external global %struct.NotCXX14Aggregate
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; CHECK-LABEL: call_copy_notcxx14aggregate:
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define void @call_copy_notcxx14aggregate() {
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%x = alloca %struct.NotCXX14Aggregate
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call void @copy_notcxx14aggregate(%struct.NotCXX14Aggregate* %x, %struct.NotCXX14Aggregate* @NotCXX14Aggregate)
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%x1 = load %struct.NotCXX14Aggregate, %struct.NotCXX14Aggregate* %x
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store %struct.NotCXX14Aggregate %x1, %struct.NotCXX14Aggregate* @NotCXX14Aggregate
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ret void
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; CHECK: bl copy_notcxx14aggregate
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; CHECK-NEXT: ldp {{.*}}, {{.*}}, [sp]
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}
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@NotPod = external global %struct.NotPod
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; CHECK-LABEL: call_copy_notpod:
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define void @call_copy_notpod() {
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%x = call [2 x i64] @copy_notpod(%struct.NotPod* @NotPod)
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%notpod = bitcast %struct.NotPod* @NotPod to [2 x i64]*
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store [2 x i64] %x, [2 x i64]* %notpod
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ret void
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; CHECK: bl copy_notpod
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; CHECK-NEXT: stp x0, x1, [{{.*}}]
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}
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