adec922361
We would like to start pushing -mcpu=generic towards enabling the set of
features that improves performance for some CPUs, without hurting any
others. A blend of the performance options hopefully beneficial to all
CPUs. The largest part of that is enabling in-order scheduling using the
Cortex-A55 schedule model. This is similar to the Arm backend change
from eecb353d0e which made -mcpu=generic perform in-order scheduling
using the cortex-a8 schedule model.
The idea is that in-order cpu's require the most help in instruction
scheduling, whereas out-of-order cpus can for the most part out-of-order
schedule around different codegen. Our benchmarking suggests that
hypothesis holds. When running on an in-order core this improved
performance by 3.8% geomean on a set of DSP workloads, 2% geomean on
some other embedded benchmark and between 1% and 1.8% on a set of
singlecore and multicore workloads, all running on a Cortex-A55 cluster.
On an out-of-order cpu the results are a lot more noisy but show flat
performance or an improvement. On the set of DSP and embedded
benchmarks, run on a Cortex-A78 there was a very noisy 1% speed
improvement. Using the most detailed results I could find, SPEC2006 runs
on a Neoverse N1 show a small increase in instruction count (+0.127%),
but a decrease in cycle counts (-0.155%, on average). The instruction
count is very low noise, the cycle count is more noisy with a 0.15%
decrease not being significant. SPEC2k17 shows a small decrease (-0.2%)
in instruction count leading to a -0.296% decrease in cycle count. These
results are within noise margins but tend to show a small improvement in
general.
When specifying an Apple target, clang will set "-target-cpu apple-a7"
on the command line, so should not be affected by this change when
running from clang. This also doesn't enable more runtime unrolling like
-mcpu=cortex-a55 does, only changing the schedule used.
A lot of existing tests have updated. This is a summary of the important
differences:
- Most changes are the same instructions in a different order.
- Sometimes this leads to very minor inefficiencies, such as requiring
an extra mov to move variables into r0/v0 for the return value of a test
function.
- misched-fusion.ll was no longer fusing the pairs of instructions it
should, as per D110561. I've changed the schedule used in the test
for now.
- neon-mla-mls.ll now uses "mul; sub" as opposed to "neg; mla" due to
the different latencies. This seems fine to me.
- Some SVE tests do not always remove movprfx where they did before due
to different register allocation giving different destructive forms.
- The tests argument-blocks-array-of-struct.ll and arm64-windows-calls.ll
produce two LDR where they previously produced an LDP due to
store-pair-suppress kicking in.
- arm64-ldp.ll and arm64-neon-copy.ll are missing pre/postinc on LPD.
- Some tests such as arm64-neon-mul-div.ll and
ragreedy-local-interval-cost.ll have more, less or just different
spilling.
- In aarch64_generated_funcs.ll.generated.expected one part of the
function is no longer outlined. Interestingly if I switch this to use
any other scheduled even less is outlined.
Some of these are expected to happen, such as differences in outlining
or register spilling. There will be places where these result in worse
codegen, places where they are better, with the SPEC instruction counts
suggesting it is not a decrease overall, on average.
Differential Revision: https://reviews.llvm.org/D110830
145 lines
8.5 KiB
LLVM
145 lines
8.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-none-unknown-linuxeabi -consthoist-gep %s -o - | FileCheck %s
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; RUN: llc -mtriple=aarch64-none-unknown-linuxeabi -consthoist-gep -opaque-pointers %s -o - | FileCheck %s
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%struct.blam = type { %struct.bar, %struct.bar.0, %struct.wobble, %struct.wombat, i8, i16, %struct.snork.2, %struct.foo, %struct.snork.3, %struct.wobble.4, %struct.quux, [9 x i16], %struct.spam, %struct.zot }
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%struct.bar = type { i8, i8, %struct.snork }
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%struct.snork = type { i16, i8, i8 }
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%struct.bar.0 = type { i8, i8, i16, i8, i8, %struct.barney }
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%struct.barney = type { i8, i8, i8, i8 }
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%struct.wobble = type { i8, i8, %struct.eggs, %struct.bar.1 }
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%struct.eggs = type { i8, i8, i8 }
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%struct.bar.1 = type { i8, i8, i8, i8 }
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%struct.wombat = type { i8, i8, i16, i32, i32, i32, i32 }
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%struct.snork.2 = type { i8, i8, i8 }
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%struct.foo = type { [12 x i32], [12 x i32], [4 x i32], i8, i8, i8, i8, i8, i8, i8, i8 }
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%struct.snork.3 = type { i16, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i16 }
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%struct.wobble.4 = type { i32, i32, i32, i32, i32, i32, i16, i16, i8, i8, i16, i32, i32, i16, i8, i8 }
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%struct.quux = type { i32, %struct.foo.5, i8, i8, i8, i8, i32, %struct.snork.6, %struct.foo.7, [16 x i8], i16, i16, i8, i8, i8, i8, i32, i32, i32 }
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%struct.foo.5 = type { i16, i8, i8 }
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%struct.snork.6 = type { i16, i8, i8 }
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%struct.foo.7 = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
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%struct.spam = type { i8, i8 }
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%struct.zot = type { [5 x i32], [3 x i32], [6 x i32], [3 x i32], [2 x i32], [4 x i32], [3 x i32], [2 x i32], [4 x i32], [5 x i32], [3 x i32], [6 x i32], [1 x i32], i32, i32, i32, i32, i32, i32 }
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@global = external dso_local local_unnamed_addr global %struct.blam, align 4
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; Function Attrs: norecurse nounwind optsize ssp
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define dso_local void @blam() local_unnamed_addr #0 {
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; CHECK-LABEL: blam:
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; CHECK: // %bb.0: // %bb
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; CHECK-NEXT: adrp x8, global+174
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; CHECK-NEXT: add x8, x8, :lo12:global+174
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; CHECK-NEXT: ldrb w9, [x8]
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; CHECK-NEXT: tbnz w9, #0, .LBB0_2
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; CHECK-NEXT: // %bb.1: // %bb3
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; CHECK-NEXT: mov w9, #44032
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; CHECK-NEXT: movk w9, #12296, lsl #16
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; CHECK-NEXT: orr w11, w9, #0x4
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; CHECK-NEXT: ldr w10, [x9]
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; CHECK-NEXT: stur w10, [x8, #158]
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; CHECK-NEXT: ldr w10, [x11]
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; CHECK-NEXT: orr w11, w9, #0x8
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; CHECK-NEXT: and w10, w10, #0xffff
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; CHECK-NEXT: stur w10, [x8, #162]
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; CHECK-NEXT: ldr w10, [x11]
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; CHECK-NEXT: orr w11, w9, #0xc
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; CHECK-NEXT: and w10, w10, #0x1f1f1f1f
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; CHECK-NEXT: stur w10, [x8, #166]
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; CHECK-NEXT: ldr w10, [x11]
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; CHECK-NEXT: mov w11, #172
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; CHECK-NEXT: orr w11, w9, w11
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; CHECK-NEXT: and w10, w10, #0x1f1f1f1f
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; CHECK-NEXT: stur w10, [x8, #170]
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; CHECK-NEXT: mov w10, #176
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; CHECK-NEXT: ldr w8, [x11]
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; CHECK-NEXT: adrp x11, global+528
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; CHECK-NEXT: add x11, x11, :lo12:global+528
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; CHECK-NEXT: orr w10, w9, w10
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; CHECK-NEXT: and w8, w8, #0xffffff
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; CHECK-NEXT: str w8, [x11]
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; CHECK-NEXT: ldr w8, [x10]
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; CHECK-NEXT: mov w10, #180
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; CHECK-NEXT: orr w10, w9, w10
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; CHECK-NEXT: and w8, w8, #0xffffff
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; CHECK-NEXT: str w8, [x11, #4]
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; CHECK-NEXT: ldr w8, [x10]
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; CHECK-NEXT: mov w10, #184
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; CHECK-NEXT: orr w9, w9, w10
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; CHECK-NEXT: and w8, w8, #0xffffff
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; CHECK-NEXT: str w8, [x11, #8]
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; CHECK-NEXT: ldr w8, [x9]
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; CHECK-NEXT: and w8, w8, #0xffffff
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; CHECK-NEXT: str w8, [x11, #12]
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; CHECK-NEXT: .LBB0_2: // %bb19
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; CHECK-NEXT: ret
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bb:
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%tmp = load i8, i8* getelementptr inbounds (%struct.blam, %struct.blam* @global, i32 0, i32 7, i32 9), align 2, !tbaa !3
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%tmp1 = and i8 %tmp, 1
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%tmp2 = icmp eq i8 %tmp1, 0
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br i1 %tmp2, label %bb3, label %bb19
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bb3: ; preds = %bb
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%tmp4 = load volatile i32, i32* inttoptr (i32 805874688 to i32*), align 1024, !tbaa !23
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store i32 %tmp4, i32* getelementptr inbounds (%struct.blam, %struct.blam* @global, i32 0, i32 13, i32 0, i32 0), align 4, !tbaa !23
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%tmp5 = load volatile i32, i32* inttoptr (i32 805874692 to i32*), align 4, !tbaa !23
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%tmp6 = and i32 %tmp5, 65535
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store i32 %tmp6, i32* getelementptr inbounds (%struct.blam, %struct.blam* @global, i32 0, i32 13, i32 0, i32 1), align 4, !tbaa !23
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%tmp7 = load volatile i32, i32* inttoptr (i32 805874696 to i32*), align 8, !tbaa !23
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%tmp8 = and i32 %tmp7, 522133279
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store i32 %tmp8, i32* getelementptr inbounds (%struct.blam, %struct.blam* @global, i32 0, i32 13, i32 0, i32 2), align 4, !tbaa !23
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%tmp9 = load volatile i32, i32* inttoptr (i32 805874700 to i32*), align 4, !tbaa !23
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%tmp10 = and i32 %tmp9, 522133279
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store i32 %tmp10, i32* getelementptr inbounds (%struct.blam, %struct.blam* @global, i32 0, i32 13, i32 0, i32 3), align 4, !tbaa !23
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%tmp11 = load volatile i32, i32* inttoptr (i32 805874860 to i32*), align 4, !tbaa !23
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%tmp12 = and i32 %tmp11, 16777215
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store i32 %tmp12, i32* getelementptr inbounds (%struct.blam, %struct.blam* @global, i32 0, i32 13, i32 15), align 4, !tbaa !24
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%tmp13 = load volatile i32, i32* inttoptr (i32 805874864 to i32*), align 16, !tbaa !23
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%tmp14 = and i32 %tmp13, 16777215
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store i32 %tmp14, i32* getelementptr inbounds (%struct.blam, %struct.blam* @global, i32 0, i32 13, i32 16), align 4, !tbaa !25
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%tmp15 = load volatile i32, i32* inttoptr (i32 805874868 to i32*), align 4, !tbaa !23
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%tmp16 = and i32 %tmp15, 16777215
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store i32 %tmp16, i32* getelementptr inbounds (%struct.blam, %struct.blam* @global, i32 0, i32 13, i32 17), align 4, !tbaa !26
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%tmp17 = load volatile i32, i32* inttoptr (i32 805874872 to i32*), align 8, !tbaa !23
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%tmp18 = and i32 %tmp17, 16777215
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store i32 %tmp18, i32* getelementptr inbounds (%struct.blam, %struct.blam* @global, i32 0, i32 13, i32 18), align 4, !tbaa !27
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br label %bb19
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bb19: ; preds = %bb3, %bb
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ret void
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}
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attributes #0 = { norecurse nounwind optsize ssp "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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!llvm.module.flags = !{!0, !1}
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!llvm.ident = !{!2}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 1, !"min_enum_size", i32 1}
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!2 = !{!"Snapdragon LLVM ARM Compiler 8.0.0 (based on LLVM 8.0.0)"}
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!3 = !{!4, !6, i64 174}
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!4 = !{!"", !5, i64 0, !10, i64 6, !12, i64 16, !14, i64 28, !6, i64 48, !9, i64 50, !13, i64 52, !16, i64 56, !17, i64 176, !18, i64 196, !19, i64 240, !6, i64 312, !21, i64 330, !22, i64 332}
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!5 = !{!"", !6, i64 0, !6, i64 1, !8, i64 2}
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!6 = !{!"omnipotent char", !7, i64 0}
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!7 = !{!"Simple C/C++ TBAA"}
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!8 = !{!"", !9, i64 0, !6, i64 2, !6, i64 3}
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!9 = !{!"short", !6, i64 0}
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!10 = !{!"", !6, i64 0, !6, i64 1, !9, i64 2, !6, i64 4, !6, i64 5, !11, i64 6}
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!11 = !{!"", !6, i64 0, !6, i64 1, !6, i64 2, !6, i64 3}
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!12 = !{!"", !6, i64 0, !6, i64 1, !13, i64 2, !11, i64 5}
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!13 = !{!"", !6, i64 0, !6, i64 1, !6, i64 2}
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!14 = !{!"", !6, i64 0, !6, i64 1, !9, i64 2, !15, i64 4, !15, i64 8, !15, i64 12, !15, i64 16}
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!15 = !{!"long", !6, i64 0}
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!16 = !{!"", !6, i64 0, !6, i64 48, !6, i64 96, !6, i64 112, !6, i64 113, !6, i64 114, !6, i64 115, !6, i64 116, !6, i64 117, !6, i64 118, !6, i64 119}
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!17 = !{!"", !9, i64 0, !6, i64 2, !6, i64 3, !6, i64 4, !6, i64 5, !6, i64 6, !6, i64 7, !6, i64 8, !6, i64 9, !6, i64 10, !6, i64 11, !6, i64 12, !6, i64 13, !6, i64 14, !6, i64 15, !9, i64 16}
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!18 = !{!"", !15, i64 0, !15, i64 4, !15, i64 8, !15, i64 12, !15, i64 16, !15, i64 20, !9, i64 24, !9, i64 26, !6, i64 28, !6, i64 29, !9, i64 30, !15, i64 32, !15, i64 36, !9, i64 40, !6, i64 42, !6, i64 43}
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!19 = !{!"", !15, i64 0, !8, i64 4, !6, i64 8, !6, i64 9, !6, i64 10, !6, i64 11, !15, i64 12, !8, i64 16, !20, i64 20, !6, i64 36, !9, i64 52, !9, i64 54, !6, i64 56, !6, i64 57, !6, i64 58, !6, i64 59, !15, i64 60, !15, i64 64, !15, i64 68}
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!20 = !{!"", !6, i64 0, !6, i64 1, !6, i64 2, !6, i64 3, !6, i64 4, !6, i64 5, !6, i64 6, !6, i64 7, !6, i64 8, !6, i64 9, !6, i64 10, !6, i64 11, !6, i64 12, !6, i64 13, !6, i64 14, !6, i64 15}
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!21 = !{!"", !6, i64 0, !6, i64 1}
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!22 = !{!"", !6, i64 0, !6, i64 20, !6, i64 32, !6, i64 56, !6, i64 68, !6, i64 76, !6, i64 92, !6, i64 104, !6, i64 112, !6, i64 128, !6, i64 148, !6, i64 160, !6, i64 184, !15, i64 188, !15, i64 192, !15, i64 196, !15, i64 200, !15, i64 204, !15, i64 208}
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!23 = !{!15, !15, i64 0}
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!24 = !{!4, !15, i64 528}
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!25 = !{!4, !15, i64 532}
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!26 = !{!4, !15, i64 536}
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!27 = !{!4, !15, i64 540}
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