50a97aacac
Re-commit of 32e8b550e5
This patch rearranges emission of CFI instructions, so the resulting
DWARF and `.eh_frame` information is precise at every instruction.
The current state is that the unwind info is emitted only after the
function prologue. This is fine for synchronous (e.g. C++) exceptions,
but the information is generally incorrect when the program counter is
at an instruction in the prologue or the epilogue, for example:
```
stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
mov x29, sp
.cfi_def_cfa w29, 16
...
```
after the `stp` is executed the (initial) rule for the CFA still says
the CFA is in the `sp`, even though it's already offset by 16 bytes
A correct unwind info could look like:
```
stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
.cfi_def_cfa_offset 16
mov x29, sp
.cfi_def_cfa w29, 16
...
```
Having this information precise up to an instruction is useful for
sampling profilers that would like to get a stack backtrace. The end
goal (towards this patch is just a step) is to have fully working
`-fasynchronous-unwind-tables`.
Reviewed By: danielkiss, MaskRay
Differential Revision: https://reviews.llvm.org/D111411
71 lines
2.6 KiB
LLVM
71 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu cortex-a53 < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-i128:128-n8:16:32:64-S128"
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target triple = "aarch64--linux-gnu"
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declare void @f(i8*, i8*)
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declare void @f2(i8*, i8*)
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declare void @_Z5setupv()
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declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) #3
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define i32 @main() local_unnamed_addr #1 {
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; Make sure the stores happen in the correct order (the exact instructions could change).
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; CHECK-LABEL: main:
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; CHECK: // %bb.0: // %for.body.lr.ph.i.i.i.i.i.i63
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; CHECK-NEXT: sub sp, sp, #112
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; CHECK-NEXT: .cfi_def_cfa_offset 112
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; CHECK-NEXT: str x30, [sp, #96] // 8-byte Folded Spill
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; CHECK-NEXT: .cfi_offset w30, -16
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; CHECK-NEXT: bl _Z5setupv
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; CHECK-NEXT: movi v0.4s, #1
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; CHECK-NEXT: mov w9, #1
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; CHECK-NEXT: add x0, sp, #48
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; CHECK-NEXT: mov x1, sp
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; CHECK-NEXT: str xzr, [sp, #80]
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; CHECK-NEXT: str w9, [sp, #80]
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; CHECK-NEXT: stp q0, q0, [sp, #48]
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; CHECK-NEXT: ldr w8, [sp, #48]
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; CHECK-NEXT: cmp w8, #1
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; CHECK-NEXT: b.ne .LBB0_2
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; CHECK-NEXT: // %bb.1: // %for.inc
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; CHECK-NEXT: bl f
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; CHECK-NEXT: b .LBB0_3
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; CHECK-NEXT: .LBB0_2: // %if.then
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; CHECK-NEXT: bl f2
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; CHECK-NEXT: .LBB0_3: // %common.ret
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; CHECK-NEXT: ldr x30, [sp, #96] // 8-byte Folded Reload
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: add sp, sp, #112
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; CHECK-NEXT: ret
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for.body.lr.ph.i.i.i.i.i.i63:
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%b1 = alloca [10 x i32], align 16
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%x0 = bitcast [10 x i32]* %b1 to i8*
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%b2 = alloca [10 x i32], align 16
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%x1 = bitcast [10 x i32]* %b2 to i8*
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tail call void @_Z5setupv()
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%x2 = getelementptr inbounds [10 x i32], [10 x i32]* %b1, i64 0, i64 6
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%x3 = bitcast i32* %x2 to i8*
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call void @llvm.memset.p0i8.i64(i8* align 8 %x3, i8 0, i64 16, i1 false)
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%arraydecay2 = getelementptr inbounds [10 x i32], [10 x i32]* %b1, i64 0, i64 0
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%x4 = bitcast [10 x i32]* %b1 to <4 x i32>*
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store <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32>* %x4, align 16
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%incdec.ptr.i7.i.i.i.i.i.i64.3 = getelementptr inbounds [10 x i32], [10 x i32]* %b1, i64 0, i64 4
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%x5 = bitcast i32* %incdec.ptr.i7.i.i.i.i.i.i64.3 to <4 x i32>*
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store <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32>* %x5, align 16
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%incdec.ptr.i7.i.i.i.i.i.i64.7 = getelementptr inbounds [10 x i32], [10 x i32]* %b1, i64 0, i64 8
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store i32 1, i32* %incdec.ptr.i7.i.i.i.i.i.i64.7, align 16
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%x6 = load i32, i32* %arraydecay2, align 16
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%cmp6 = icmp eq i32 %x6, 1
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br i1 %cmp6, label %for.inc, label %if.then
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for.inc:
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call void @f(i8* %x0, i8* %x1)
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ret i32 0
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if.then:
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call void @f2(i8* %x0, i8* %x1)
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ret i32 0
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}
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