50a97aacac
Re-commit of 32e8b550e5
This patch rearranges emission of CFI instructions, so the resulting
DWARF and `.eh_frame` information is precise at every instruction.
The current state is that the unwind info is emitted only after the
function prologue. This is fine for synchronous (e.g. C++) exceptions,
but the information is generally incorrect when the program counter is
at an instruction in the prologue or the epilogue, for example:
```
stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
mov x29, sp
.cfi_def_cfa w29, 16
...
```
after the `stp` is executed the (initial) rule for the CFA still says
the CFA is in the `sp`, even though it's already offset by 16 bytes
A correct unwind info could look like:
```
stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
.cfi_def_cfa_offset 16
mov x29, sp
.cfi_def_cfa w29, 16
...
```
Having this information precise up to an instruction is useful for
sampling profilers that would like to get a stack backtrace. The end
goal (towards this patch is just a step) is to have fully working
`-fasynchronous-unwind-tables`.
Reviewed By: danielkiss, MaskRay
Differential Revision: https://reviews.llvm.org/D111411
140 lines
4.1 KiB
LLVM
140 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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; ANDV
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define i1 @andv_nxv32i1(<vscale x 32 x i1> %a) {
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; CHECK-LABEL: andv_nxv32i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p2.b
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; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
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; CHECK-NEXT: not p0.b, p2/z, p0.b
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; CHECK-NEXT: ptest p2, p0.b
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%res = call i1 @llvm.vector.reduce.and.nxv32i1(<vscale x 32 x i1> %a)
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ret i1 %res
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}
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define i1 @andv_nxv64i1(<vscale x 64 x i1> %a) {
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; CHECK-LABEL: andv_nxv64i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
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; CHECK-NEXT: and p1.b, p1/z, p1.b, p3.b
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; CHECK-NEXT: and p0.b, p0/z, p0.b, p2.b
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; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Folded Spill
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; CHECK-NEXT: ptrue p4.b
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; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
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; CHECK-NEXT: not p0.b, p4/z, p0.b
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; CHECK-NEXT: ptest p4, p0.b
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; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Folded Reload
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%res = call i1 @llvm.vector.reduce.and.nxv64i1(<vscale x 64 x i1> %a)
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ret i1 %res
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}
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; ORV
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define i1 @orv_nxv32i1(<vscale x 32 x i1> %a) {
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; CHECK-LABEL: orv_nxv32i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
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; CHECK-NEXT: ptest p0, p0.b
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%res = call i1 @llvm.vector.reduce.or.nxv32i1(<vscale x 32 x i1> %a)
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ret i1 %res
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}
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; XORV
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define i1 @xorv_nxv32i1(<vscale x 32 x i1> %a) {
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; CHECK-LABEL: xorv_nxv32i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p2.b
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; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b
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; CHECK-NEXT: cntp x8, p2, p0.b
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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%res = call i1 @llvm.vector.reduce.xor.nxv32i1(<vscale x 32 x i1> %a)
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ret i1 %res
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}
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; SMAXV
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define i1 @smaxv_nxv32i1(<vscale x 32 x i1> %a) {
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; CHECK-LABEL: smaxv_nxv32i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p2.b
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; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
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; CHECK-NEXT: not p0.b, p2/z, p0.b
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; CHECK-NEXT: ptest p2, p0.b
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%res = call i1 @llvm.vector.reduce.smax.nxv32i1(<vscale x 32 x i1> %a)
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ret i1 %res
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}
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; SMINV
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define i1 @sminv_nxv32i1(<vscale x 32 x i1> %a) {
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; CHECK-LABEL: sminv_nxv32i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
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; CHECK-NEXT: ptest p0, p0.b
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%res = call i1 @llvm.vector.reduce.smin.nxv32i1(<vscale x 32 x i1> %a)
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ret i1 %res
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}
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; UMAXV
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define i1 @umaxv_nxv32i1(<vscale x 32 x i1> %a) {
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; CHECK-LABEL: umaxv_nxv32i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
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; CHECK-NEXT: ptest p0, p0.b
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%res = call i1 @llvm.vector.reduce.umax.nxv32i1(<vscale x 32 x i1> %a)
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ret i1 %res
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}
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; UMINV
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define i1 @uminv_nxv32i1(<vscale x 32 x i1> %a) {
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; CHECK-LABEL: uminv_nxv32i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p2.b
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; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
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; CHECK-NEXT: not p0.b, p2/z, p0.b
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; CHECK-NEXT: ptest p2, p0.b
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%res = call i1 @llvm.vector.reduce.umin.nxv32i1(<vscale x 32 x i1> %a)
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ret i1 %res
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}
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declare i1 @llvm.vector.reduce.and.nxv32i1(<vscale x 32 x i1>)
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declare i1 @llvm.vector.reduce.and.nxv64i1(<vscale x 64 x i1>)
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declare i1 @llvm.vector.reduce.or.nxv32i1(<vscale x 32 x i1>)
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declare i1 @llvm.vector.reduce.xor.nxv32i1(<vscale x 32 x i1>)
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declare i1 @llvm.vector.reduce.smax.nxv32i1(<vscale x 32 x i1>)
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declare i1 @llvm.vector.reduce.smin.nxv32i1(<vscale x 32 x i1>)
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declare i1 @llvm.vector.reduce.umax.nxv32i1(<vscale x 32 x i1>)
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declare i1 @llvm.vector.reduce.umin.nxv32i1(<vscale x 32 x i1>)
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