18f9351223
The compiler was generating symbols in the final code object for local branch target labels. This bloats the code object, slows down the loader, and is only used to simplify disassembly. Use '--symbolize-operands' with llvm-objdump to improve readability of the branch target operands in disassembly. Fixes: SWDEV-312223 Reviewed By: scott.linder Differential Revision: https://reviews.llvm.org/D114273
112 lines
3.5 KiB
LLVM
112 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -march=amdgcn -mcpu=hawaii -mattr=+flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; End to end tests for scalar vs. vector boolean legalization strategies.
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define amdgpu_ps float @select_vgpr_sgpr_trunc_cond(i32 inreg %a, i32 %b, i32 %c) {
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; GCN-LABEL: select_vgpr_sgpr_trunc_cond:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_and_b32 s0, 1, s0
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; GCN-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
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; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
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; GCN-NEXT: ; return to shader part epilog
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%cc = trunc i32 %a to i1
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%r = select i1 %cc, i32 %b, i32 %c
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%r.f = bitcast i32 %r to float
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ret float %r.f
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}
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define amdgpu_ps float @select_vgpr_sgpr_trunc_and_cond(i32 inreg %a.0, i32 inreg %a.1, i32 %b, i32 %c) {
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; GCN-LABEL: select_vgpr_sgpr_trunc_and_cond:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_and_b32 s0, s0, s1
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; GCN-NEXT: s_and_b32 s0, 1, s0
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; GCN-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
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; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
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; GCN-NEXT: ; return to shader part epilog
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%cc.0 = trunc i32 %a.0 to i1
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%cc.1 = trunc i32 %a.1 to i1
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%and = and i1 %cc.0, %cc.1
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%r = select i1 %and, i32 %b, i32 %c
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%r.f = bitcast i32 %r to float
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ret float %r.f
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}
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define amdgpu_ps i32 @select_sgpr_trunc_and_cond(i32 inreg %a.0, i32 inreg %a.1, i32 inreg %b, i32 inreg %c) {
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; GCN-LABEL: select_sgpr_trunc_and_cond:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_and_b32 s0, s0, s1
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; GCN-NEXT: s_and_b32 s0, s0, 1
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; GCN-NEXT: s_cmp_lg_u32 s0, 0
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; GCN-NEXT: s_cselect_b32 s0, s2, s3
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; GCN-NEXT: ; return to shader part epilog
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%cc.0 = trunc i32 %a.0 to i1
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%cc.1 = trunc i32 %a.1 to i1
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%and = and i1 %cc.0, %cc.1
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%r = select i1 %and, i32 %b, i32 %c
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ret i32 %r
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}
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define amdgpu_kernel void @sgpr_trunc_brcond(i32 %cond) {
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; GCN-LABEL: sgpr_trunc_brcond:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_load_dword s0, s[0:1], 0x9
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_xor_b32 s0, s0, -1
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; GCN-NEXT: s_and_b32 s0, s0, 1
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; GCN-NEXT: s_cmp_lg_u32 s0, 0
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; GCN-NEXT: s_cbranch_scc1 .LBB3_2
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; GCN-NEXT: ; %bb.1: ; %bb0
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: flat_store_dword v[0:1], v0
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: .LBB3_2: ; %bb1
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; GCN-NEXT: v_mov_b32_e32 v0, 1
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; GCN-NEXT: flat_store_dword v[0:1], v0
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; GCN-NEXT: s_waitcnt vmcnt(0)
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entry:
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%trunc = trunc i32 %cond to i1
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br i1 %trunc, label %bb0, label %bb1
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bb0:
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store volatile i32 0, i32 addrspace(1)* undef
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unreachable
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bb1:
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store volatile i32 1, i32 addrspace(1)* undef
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unreachable
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}
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define amdgpu_kernel void @brcond_sgpr_trunc_and(i32 %cond0, i32 %cond1) {
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; GCN-LABEL: brcond_sgpr_trunc_and:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_and_b32 s0, s0, s1
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; GCN-NEXT: s_xor_b32 s0, s0, -1
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; GCN-NEXT: s_and_b32 s0, s0, 1
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; GCN-NEXT: s_cmp_lg_u32 s0, 0
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; GCN-NEXT: s_cbranch_scc1 .LBB4_2
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; GCN-NEXT: ; %bb.1: ; %bb0
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: flat_store_dword v[0:1], v0
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: .LBB4_2: ; %bb1
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; GCN-NEXT: v_mov_b32_e32 v0, 1
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; GCN-NEXT: flat_store_dword v[0:1], v0
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; GCN-NEXT: s_waitcnt vmcnt(0)
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entry:
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%trunc0 = trunc i32 %cond0 to i1
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%trunc1 = trunc i32 %cond1 to i1
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%and = and i1 %trunc0, %trunc1
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br i1 %and, label %bb0, label %bb1
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bb0:
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store volatile i32 0, i32 addrspace(1)* undef
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unreachable
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bb1:
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store volatile i32 1, i32 addrspace(1)* undef
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unreachable
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}
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