04fff547e2
Currently the return address ABI registers s[30:31], which fall in the call clobbered register range, are added as a live-in on the function entry to preserve its value when we have calls so that it gets saved and restored around the calls. But the DWARF unwind information (CFI) needs to track where the return address resides in a frame and the above approach makes it difficult to track the return address when the CFI information is emitted during the frame lowering, due to the involvment of understanding the control flow. This patch moves the return address ABI registers s[30:31] into callee saved registers range and stops adding live-in for return address registers, so that the CFI machinery will know where the return address resides when CSR save/restore happen during the frame lowering. And doing the above poses an issue that now the return instruction uses undefined register `sgpr30_sgpr31`. This is resolved by hiding the return address register use by the return instruction through the `SI_RETURN` pseudo instruction, which doesn't take any input operands, until the `SI_RETURN` pseudo gets lowered to the `S_SETPC_B64_return` during the `expandPostRAPseudo()`. As an added benefit, this patch simplifies overall return instruction handling. Note: The AMDGPU CFI changes are there only in the downstream code and another version of this patch will be posted for review for the downstream code. Reviewed By: arsenm, ronlieb Differential Revision: https://reviews.llvm.org/D114652
184 lines
8.8 KiB
LLVM
184 lines
8.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -global-isel -global-isel-abort=2 -pass-remarks-missed='gisel*' -march=amdgcn -mcpu=fiji -stop-after=irtranslator -verify-machineinstrs %s -o - 2>%t | FileCheck %s
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; RUN: FileCheck -check-prefix=ERR %s < %t
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; ERR: remark: <unknown>:0:0: unable to translate instruction: call: ' %sgpr = call <4 x i32> asm sideeffect "; def $0", "={s[8:12]}"()' (in function: return_type_is_too_big_vector)
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; ERR: remark: <unknown>:0:0: unable to translate instruction: call: ' %reg = call i64 asm sideeffect "; def $0", "={v8}"()' (in function: return_type_is_too_big_scalar)
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; ERR: remark: <unknown>:0:0: unable to translate instruction: call: ' %reg = call i8 addrspace(1)* asm sideeffect "; def $0", "={v8}"()' (in function: return_type_is_too_big_pointer)
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; ERR: remark: <unknown>:0:0: unable to translate instruction: call: ' %reg = call i8 addrspace(3)* asm sideeffect "; def $0", "={v[8:9]}"()' (in function: return_type_is_too_small_pointer)
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; ERR: remark: <unknown>:0:0: unable to translate instruction: call: ' call void asm sideeffect "; use $0", "{v[0:9]}"(<8 x i32> %arg)' (in function: use_vector_too_big)
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; ERR: remark: <unknown>:0:0: unable to translate instruction: call: ' call void asm sideeffect "; use $0", "{v0}"(i64 %arg)' (in function: use_scalar_too_small)
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; ERR: remark: <unknown>:0:0: unable to translate instruction: call: ' call void asm sideeffect "; use $0", "{v0}"(i8 addrspace(1)* %arg)' (in function: use_pointer_too_small)
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; ERR: remark: <unknown>:0:0: unable to translate instruction: call: ' call void asm sideeffect "; use $0", "{v[0:1]}"(i32 addrspace(3)* %arg)' (in function: use_pointer_too_big)
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; This asm is broken because it's using a 5 element wide physical
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; register for a 4 element wide value. Make sure we don't crash, and
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; take the IR type as truth.
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define amdgpu_kernel void @return_type_is_too_big_vector() {
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; CHECK-LABEL: name: return_type_is_too_big_vector
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1 (%ir-block.0):
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; CHECK-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12
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%sgpr = call <4 x i32> asm sideeffect "; def $0", "={s[8:12]}" ()
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call void asm sideeffect "; use $0", "s"(<4 x i32> %sgpr) #0
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ret void
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}
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; FIXME: This is crashing in the DAG
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; define amdgpu_kernel void @return_type_is_too_small_vector() {
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; %sgpr = call <4 x i32> asm sideeffect "; def $0", "={s[8:10]}" ()
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; call void asm sideeffect "; use $0", "s"(<4 x i32> %sgpr) #0
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; ret void
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; }
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define i64 @return_type_is_too_big_scalar() {
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; CHECK-LABEL: name: return_type_is_too_big_scalar
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1 (%ir-block.0):
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; CHECK-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $vgpr8
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%reg = call i64 asm sideeffect "; def $0", "={v8}" ()
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ret i64 %reg
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}
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define i32 @return_type_is_too_small_scalar() {
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; CHECK-LABEL: name: return_type_is_too_small_scalar
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $vgpr8_vgpr9
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr8_vgpr9
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
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; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
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; CHECK-NEXT: SI_RETURN implicit $vgpr0
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%reg = call i32 asm sideeffect "; def $0", "={v[8:9]}" ()
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ret i32 %reg
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}
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define i8 addrspace(1)* @return_type_is_too_big_pointer() {
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; CHECK-LABEL: name: return_type_is_too_big_pointer
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1 (%ir-block.0):
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; CHECK-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $vgpr8
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%reg = call i8 addrspace(1)* asm sideeffect "; def $0", "={v8}" ()
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ret i8 addrspace(1)* %reg
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}
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define i8 addrspace(3)* @return_type_is_too_small_pointer() {
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; CHECK-LABEL: name: return_type_is_too_small_pointer
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1 (%ir-block.0):
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; CHECK-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $vgpr8_vgpr9
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%reg = call i8 addrspace(3)* asm sideeffect "; def $0", "={v[8:9]}" ()
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ret i8 addrspace(3)* %reg
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}
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define void @use_vector_too_small(<8 x i32> %arg) {
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; CHECK-LABEL: name: use_vector_too_small
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
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; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
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; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
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; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<8 x s32>)
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; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 9 /* reguse */, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
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; CHECK-NEXT: SI_RETURN
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call void asm sideeffect "; use $0", "{v[0:7]}"(<8 x i32> %arg)
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ret void
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}
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define void @use_vector_too_big(<8 x i32> %arg) {
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; CHECK-LABEL: name: use_vector_too_big
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
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; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
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; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1 (%ir-block.0):
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call void asm sideeffect "; use $0", "{v[0:9]}"(<8 x i32> %arg)
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ret void
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}
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define void @use_scalar_too_small(i64 %arg) {
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; CHECK-LABEL: name: use_scalar_too_small
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1 (%ir-block.0):
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call void asm sideeffect "; use $0", "{v0}"(i64 %arg)
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ret void
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}
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define void @use_scalar_too_big(i32 %arg) {
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; CHECK-LABEL: name: use_scalar_too_big
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
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; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
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; CHECK-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 9 /* reguse */, $vgpr0_vgpr1
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; CHECK-NEXT: SI_RETURN
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call void asm sideeffect "; use $0", "{v[0:1]}"(i32 %arg)
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ret void
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}
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define void @use_pointer_too_small(i8 addrspace(1)* %arg) {
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; CHECK-LABEL: name: use_pointer_too_small
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1 (%ir-block.0):
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call void asm sideeffect "; use $0", "{v0}"(i8 addrspace(1)* %arg)
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ret void
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}
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define void @use_pointer_too_big(i32 addrspace(3)* %arg) {
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; CHECK-LABEL: name: use_pointer_too_big
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1 (%ir-block.0):
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call void asm sideeffect "; use $0", "{v[0:1]}"(i32 addrspace(3)* %arg)
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ret void
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}
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