aa2d3b59ce
Register operands with superclasses can possibly have multiple regBanks if they have different register types. The regBank ambiguity resolved during regbankselect should be used to constrain the operand regclass instead of obtaining one from the MCInstrDesc. This is a prerequisite patch for D109300 that introduces allocatable AV_* Superclasses for AMDGPU by combining both VGPRs and AGPRs and we want to restrain the regclass to either A or V based on the incoming regbank. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D112323
168 lines
6.5 KiB
YAML
168 lines
6.5 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE32 %s
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---
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name: class_s32_vcc_sv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; WAVE64-LABEL: name: class_s32_vcc_sv
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; WAVE64: liveins: $sgpr0, $vgpr0
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; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
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; WAVE32-LABEL: name: class_s32_vcc_sv
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; WAVE32: liveins: $sgpr0, $vgpr0
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; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: class_s32_vcc_vs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; WAVE64-LABEL: name: class_s32_vcc_vs
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; WAVE64: liveins: $sgpr0, $vgpr0
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
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; WAVE32-LABEL: name: class_s32_vcc_vs
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; WAVE32: liveins: $sgpr0, $vgpr0
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; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: class_s32_vcc_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; WAVE64-LABEL: name: class_s32_vcc_vv
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; WAVE64: liveins: $vgpr0, $vgpr1
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
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; WAVE32-LABEL: name: class_s32_vcc_vv
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; WAVE32: liveins: $vgpr0, $vgpr1
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; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: class_s64_vcc_sv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $vgpr0
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; WAVE64-LABEL: name: class_s64_vcc_sv
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; WAVE64: liveins: $sgpr0_sgpr1, $vgpr0
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; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
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; WAVE32-LABEL: name: class_s64_vcc_sv
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; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0
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; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:vgpr(s32) = COPY $vgpr0
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%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: class_s64_vcc_vs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $vgpr0
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; WAVE64-LABEL: name: class_s64_vcc_vs
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; WAVE64: liveins: $sgpr0_sgpr1, $vgpr0
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; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
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; WAVE32-LABEL: name: class_s64_vcc_vs
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; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0
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; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%1:sgpr(s32) = COPY $sgpr0
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%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: class_s64_vcc_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2
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; WAVE64-LABEL: name: class_s64_vcc_vv
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; WAVE64: liveins: $vgpr0_vgpr1, $vgpr2
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; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
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; WAVE32-LABEL: name: class_s64_vcc_vv
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; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2
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; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%1:vgpr(s32) = COPY $vgpr2
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%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
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S_ENDPGM 0, implicit %2
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...
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