da067ed569
Using a BufferSize of one for memory ProcResources will result in better ILP since it more accurately models the dependencies between memory ops and their consumers on an in-order processor. After this change, the scheduler will treat the data edges from loads as blocking so that stalls are guaranteed when waiting for data to be retreaved from memory. Since we don't actually track waitcnt here, this should do a better job at modeling their behavior. Practically, this means that the scheduler will trigger the 'STALL' heuristic more often. This type of change needs to be evaluated experimentally. Preliminary results are positive. Fixes: SWDEV-282962 Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D114777
82 lines
3.7 KiB
LLVM
82 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
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; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
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define amdgpu_kernel void @dpp_test(i32 addrspace(1)* %out, i32 %in1, i32 %in2) {
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; GFX8-LABEL: dpp_test:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
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; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: v_mov_b32_e32 v2, s2
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; GFX8-NEXT: v_mov_b32_e32 v0, s3
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; GFX8-NEXT: s_nop 1
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; GFX8-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
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; GFX8-NEXT: v_mov_b32_e32 v0, s0
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; GFX8-NEXT: v_mov_b32_e32 v1, s1
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; GFX8-NEXT: flat_store_dword v[0:1], v2
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; GFX8-NEXT: s_endpgm
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;
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; GFX10-LABEL: dpp_test:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_clause 0x1
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; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
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; GFX10-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: v_mov_b32_e32 v0, s2
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; GFX10-NEXT: v_mov_b32_e32 v1, s3
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; GFX10-NEXT: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
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; GFX10-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-NEXT: global_store_dword v1, v0, s[4:5]
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; GFX10-NEXT: s_endpgm
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%tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 false)
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store i32 %tmp0, i32 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @update_dpp64_test(i64 addrspace(1)* %arg, i64 %in1, i64 %in2) {
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; GFX8-LABEL: update_dpp64_test:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; GFX8-NEXT: v_lshlrev_b32_e32 v2, 3, v0
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: v_mov_b32_e32 v0, s0
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; GFX8-NEXT: v_mov_b32_e32 v1, s1
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; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
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; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
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; GFX8-NEXT: v_mov_b32_e32 v5, s3
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; GFX8-NEXT: v_mov_b32_e32 v4, s2
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; GFX8-NEXT: s_waitcnt vmcnt(0)
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; GFX8-NEXT: v_mov_b32_dpp v5, v3 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
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; GFX8-NEXT: v_mov_b32_dpp v4, v2 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
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; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[4:5]
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; GFX8-NEXT: s_endpgm
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;
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; GFX10-LABEL: update_dpp64_test:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[0:1]
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; GFX10-NEXT: v_mov_b32_e32 v2, s2
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; GFX10-NEXT: v_mov_b32_e32 v3, s3
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
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; GFX10-NEXT: v_mov_b32_dpp v3, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
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; GFX10-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]
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; GFX10-NEXT: s_endpgm
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %id
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%load = load i64, i64 addrspace(1)* %gep
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%tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 1, i32 1, i32 1, i1 false) #1
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store i64 %tmp0, i64 addrspace(1)* %gep
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32 immarg, i32 immarg, i32 immarg, i1 immarg) #1
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declare i64 @llvm.amdgcn.update.dpp.i64(i64, i64, i32 immarg, i32 immarg, i32 immarg, i1 immarg) #1
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attributes #0 = { nounwind readnone speculatable }
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attributes #1 = { convergent nounwind readnone }
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