cf58b9ce98
While enabling vector superclasses with D109301, the AV spills are converted into VGPR spills by introducing appropriate copies. The whole thing ended up adding two instructions per spill (a copy + vgpr spill pseudo) and caused an incorrect liverange update during inline spiller. This patch adds the pseudo instructions for all AV spills from 32b to 1024b and handles them in the way all other spills are lowered. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D115439
85 lines
5.6 KiB
YAML
85 lines
5.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -start-before=greedy,1 -stop-after=prologepilog -verify-machineinstrs -verify-regalloc -o - %s | FileCheck --check-prefixes=GCN %s
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# The VGPR pair spilled and restored around the callsite is used in the next basic block.
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#
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# AMDGPU target spill hooks storeRegToStackSlot/loadRegFromStackSlot handle the register spills via
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# spill pseudos to insert a single instruction per spill to tackle the limitation during inline spiller
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# that incorrectly updates the Liveintervals in case of a spill lowered into multiple instructions.
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# AV spills were handled earlier by converting them into equivalent VGPR spills by adding appropriate copies.
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# The multiple instructions (a copy + vgpr spill pseudo) introduced an incorrect liverange that caused a
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# crash during RA. It is fixed by introducing AV* spill pseudos to ensure a single instruction per spill and
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# the test started compiling successfully.
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---
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name: test_av_spill_cross_bb_usage
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tracksRegLiveness: true
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stack:
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- { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4 }
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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stackPtrOffsetReg: '$sgpr32'
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body: |
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; GCN-LABEL: name: test_av_spill_cross_bb_usage
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; GCN: bb.0:
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; GCN: S_BRANCH %bb.1
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; GCN: bb.1:
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; GCN-NEXT: successors: %bb.2(0x80000000)
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; GCN-NEXT: liveins: $exec:0x000000000000000F, $sgpr30, $sgpr31, $vgpr0:0x0000000000000003, $vgpr1:0x0000000000000003, $vgpr2:0x0000000000000003, $vgpr3:0x0000000000000003, $vgpr4:0x0000000000000003, $vgpr5:0x0000000000000003, $vgpr6:0x0000000000000003, $vgpr7:0x0000000000000003, $vgpr8:0x0000000000000003, $vgpr9:0x0000000000000003, $vgpr10:0x0000000000000003, $vgpr11:0x0000000000000003, $vgpr40, $sgpr30_sgpr31, $vgpr14_vgpr15:0x000000000000000F, $vgpr41_vgpr42:0x000000000000000F, $vgpr43_vgpr44:0x000000000000000F, $vgpr45_vgpr46:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F
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; GCN-NEXT: {{ $}}
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; GCN: BUFFER_STORE_DWORD_OFFSET killed $vgpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, 0, implicit $exec, implicit-def $vgpr14_vgpr15, implicit $vgpr14_vgpr15 :: (store (s32) into %stack.1, addrspace 5)
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; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, 0, implicit $exec, implicit killed $vgpr14_vgpr15 :: (store (s32) into %stack.1 + 4, addrspace 5)
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; GCN-NEXT: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr16_sgpr17, 0, csr_amdgpu_highregs, implicit-def dead $vgpr0
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; GCN-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, 0, implicit $exec, implicit-def $vgpr14_vgpr15 :: (load (s32) from %stack.1, addrspace 5)
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; GCN-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, 0, implicit $exec, implicit-def $vgpr14_vgpr15 :: (load (s32) from %stack.1 + 4, addrspace 5)
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; GCN: bb.2:
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; GCN-NEXT: liveins: $vgpr40, $vgpr14_vgpr15:0x000000000000000F, $vgpr43_vgpr44:0x000000000000000F
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: renamable $vgpr0_vgpr1 = V_MOV_B64_PSEUDO 0, implicit $exec
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; GCN-NEXT: FLAT_STORE_DWORDX2 undef renamable $vgpr0_vgpr1, killed renamable $vgpr43_vgpr44, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
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; GCN-NEXT: FLAT_STORE_DWORDX2 killed renamable $vgpr0_vgpr1, killed renamable $vgpr14_vgpr15, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
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; GCN: S_SETPC_B64_return undef $sgpr30_sgpr31
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr40, $sgpr30, $sgpr31, $sgpr30_sgpr31
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undef %0.sub1:vreg_64 = COPY $vgpr15
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%0.sub0:vreg_64 = COPY $vgpr14
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undef %1.sub1:vreg_64 = COPY $vgpr13
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%1.sub0:vreg_64 = COPY $vgpr12
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undef %2.sub1:vreg_64 = COPY $vgpr11
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%2.sub0:vreg_64 = COPY $vgpr10
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undef %3.sub1:vreg_64 = COPY $vgpr9
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%3.sub0:vreg_64 = COPY $vgpr8
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undef %4.sub1:vreg_64 = COPY $vgpr7
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%4.sub0:vreg_64 = COPY $vgpr6
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undef %5.sub1:vreg_64 = COPY $vgpr5
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%5.sub0:vreg_64 = COPY $vgpr4
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undef %6.sub1:vreg_64 = COPY $vgpr3
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%6.sub0:vreg_64 = COPY $vgpr2
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undef %7.sub1:vreg_64 = COPY $vgpr1
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%7.sub0:vreg_64 = COPY $vgpr0
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S_CBRANCH_SCC1 %bb.2, implicit undef $scc
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S_BRANCH %bb.1
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bb.1:
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liveins: $vgpr40, $sgpr30, $sgpr31, $sgpr30_sgpr31
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ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
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renamable $sgpr16_sgpr17 = IMPLICIT_DEF
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$vgpr40 = V_WRITELANE_B32 $sgpr30, 0, $vgpr40, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31
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$vgpr40 = V_WRITELANE_B32 killed $sgpr31, 1, $vgpr40, implicit killed $sgpr30_sgpr31
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dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr16_sgpr17, 0, csr_amdgpu_highregs, implicit-def dead $vgpr0
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%8:vreg_64 = nofpexcept V_FMA_F64_e64 0, %7, 0, %6, 0, %5, 0, 0, implicit $mode, implicit $exec
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ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
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FLAT_STORE_DWORDX2 %4, %8, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
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FLAT_STORE_DWORDX2 %2, %3, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
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bb.2:
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liveins: $vgpr40
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%9:vreg_64 = V_MOV_B64_PSEUDO 0, implicit $exec
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FLAT_STORE_DWORDX2 undef %10:vreg_64, %1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
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FLAT_STORE_DWORDX2 %9, %0, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
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S_SETPC_B64_return undef $sgpr30_sgpr31
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...
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