da067ed569
Using a BufferSize of one for memory ProcResources will result in better ILP since it more accurately models the dependencies between memory ops and their consumers on an in-order processor. After this change, the scheduler will treat the data edges from loads as blocking so that stalls are guaranteed when waiting for data to be retreaved from memory. Since we don't actually track waitcnt here, this should do a better job at modeling their behavior. Practically, this means that the scheduler will trigger the 'STALL' heuristic more often. This type of change needs to be evaluated experimentally. Preliminary results are positive. Fixes: SWDEV-282962 Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D114777
168 lines
6.7 KiB
LLVM
168 lines
6.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; Extract the high bit of the 1st quarter
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define amdgpu_kernel void @v_uextract_bit_31_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 {
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; GCN-LABEL: v_uextract_bit_31_i128:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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; GCN-NEXT: s_ashr_i32 s3, s2, 31
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; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 4
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; GCN-NEXT: v_mov_b32_e32 v5, s1
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; GCN-NEXT: s_mov_b32 s11, 0xf000
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; GCN-NEXT: s_mov_b32 s10, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b64 s[8:9], s[6:7]
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; GCN-NEXT: v_mov_b32_e32 v4, s0
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; GCN-NEXT: buffer_load_dword v0, v[4:5], s[8:11], 0 addr64
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: v_mov_b32_e32 v2, v1
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; GCN-NEXT: s_mov_b64 s[6:7], s[10:11]
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; GCN-NEXT: v_mov_b32_e32 v3, v1
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0
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; GCN-NEXT: buffer_store_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr64
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; GCN-NEXT: s_endpgm
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%id.x = tail call i32 @llvm.amdgcn.workgroup.id.x()
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%in.gep = getelementptr i128, i128 addrspace(1)* %in, i32 %id.x
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%out.gep = getelementptr i128, i128 addrspace(1)* %out, i32 %id.x
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%ld.64 = load i128, i128 addrspace(1)* %in.gep
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%srl = lshr i128 %ld.64, 31
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%bit = and i128 %srl, 1
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store i128 %bit, i128 addrspace(1)* %out.gep
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ret void
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}
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; Extract the high bit of the 2nd quarter
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define amdgpu_kernel void @v_uextract_bit_63_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 {
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; GCN-LABEL: v_uextract_bit_63_i128:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; GCN-NEXT: s_mov_b32 s7, 0xf000
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; GCN-NEXT: s_mov_b32 s6, 0
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; GCN-NEXT: v_lshlrev_b32_e32 v4, 4, v0
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; GCN-NEXT: v_mov_b32_e32 v5, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b64 s[8:9], s[2:3]
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; GCN-NEXT: s_mov_b64 s[10:11], s[6:7]
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; GCN-NEXT: buffer_load_dword v0, v[4:5], s[8:11], 0 addr64 offset:4
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; GCN-NEXT: v_mov_b32_e32 v1, v5
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; GCN-NEXT: v_mov_b32_e32 v2, v5
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; GCN-NEXT: s_mov_b64 s[4:5], s[0:1]
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; GCN-NEXT: v_mov_b32_e32 v3, v5
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0
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; GCN-NEXT: buffer_store_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr64
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; GCN-NEXT: s_endpgm
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%id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%in.gep = getelementptr i128, i128 addrspace(1)* %in, i32 %id.x
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%out.gep = getelementptr i128, i128 addrspace(1)* %out, i32 %id.x
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%ld.64 = load i128, i128 addrspace(1)* %in.gep
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%srl = lshr i128 %ld.64, 63
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%bit = and i128 %srl, 1
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store i128 %bit, i128 addrspace(1)* %out.gep
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ret void
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}
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; Extract the high bit of the 3rd quarter
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define amdgpu_kernel void @v_uextract_bit_95_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 {
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; GCN-LABEL: v_uextract_bit_95_i128:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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; GCN-NEXT: s_ashr_i32 s3, s2, 31
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; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 4
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_mov_b32 s2, 0
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; GCN-NEXT: v_mov_b32_e32 v5, s1
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b64 s[8:9], s[6:7]
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; GCN-NEXT: s_mov_b64 s[10:11], s[2:3]
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; GCN-NEXT: v_mov_b32_e32 v4, s0
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; GCN-NEXT: buffer_load_dword v0, v[4:5], s[8:11], 0 addr64 offset:8
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: v_mov_b32_e32 v2, v1
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; GCN-NEXT: s_mov_b64 s[0:1], s[4:5]
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; GCN-NEXT: v_mov_b32_e32 v3, v1
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0
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; GCN-NEXT: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 addr64
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; GCN-NEXT: s_endpgm
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%id.x = tail call i32 @llvm.amdgcn.workgroup.id.x()
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%in.gep = getelementptr i128, i128 addrspace(1)* %in, i32 %id.x
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%out.gep = getelementptr i128, i128 addrspace(1)* %out, i32 %id.x
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%ld.64 = load i128, i128 addrspace(1)* %in.gep
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%srl = lshr i128 %ld.64, 95
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%bit = and i128 %srl, 1
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store i128 %bit, i128 addrspace(1)* %out.gep
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ret void
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}
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; Extract the high bit of the 4th quarter
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define amdgpu_kernel void @v_uextract_bit_127_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 {
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; GCN-LABEL: v_uextract_bit_127_i128:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; GCN-NEXT: s_mov_b32 s7, 0xf000
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; GCN-NEXT: s_mov_b32 s6, 0
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; GCN-NEXT: v_lshlrev_b32_e32 v4, 4, v0
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; GCN-NEXT: v_mov_b32_e32 v5, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b64 s[8:9], s[2:3]
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; GCN-NEXT: s_mov_b64 s[10:11], s[6:7]
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; GCN-NEXT: buffer_load_dword v0, v[4:5], s[8:11], 0 addr64 offset:12
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; GCN-NEXT: v_mov_b32_e32 v1, v5
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; GCN-NEXT: v_mov_b32_e32 v2, v5
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; GCN-NEXT: s_mov_b64 s[4:5], s[0:1]
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; GCN-NEXT: v_mov_b32_e32 v3, v5
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0
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; GCN-NEXT: buffer_store_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr64
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; GCN-NEXT: s_endpgm
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%id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%in.gep = getelementptr i128, i128 addrspace(1)* %in, i32 %id.x
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%out.gep = getelementptr i128, i128 addrspace(1)* %out, i32 %id.x
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%ld.64 = load i128, i128 addrspace(1)* %in.gep
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%srl = lshr i128 %ld.64, 127
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%bit = and i128 %srl, 1
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store i128 %bit, i128 addrspace(1)* %out.gep
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ret void
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}
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; Spans more than 2 dword boundaries
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define amdgpu_kernel void @v_uextract_bit_34_100_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 {
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; GCN-LABEL: v_uextract_bit_34_100_i128:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; GCN-NEXT: s_mov_b32 s7, 0xf000
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; GCN-NEXT: s_mov_b32 s6, 0
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; GCN-NEXT: v_lshlrev_b32_e32 v8, 4, v0
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; GCN-NEXT: v_mov_b32_e32 v9, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b64 s[4:5], s[2:3]
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; GCN-NEXT: buffer_load_dwordx4 v[0:3], v[8:9], s[4:7], 0 addr64
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; GCN-NEXT: s_mov_b64 s[2:3], s[6:7]
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; GCN-NEXT: v_mov_b32_e32 v7, v9
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_lshl_b64 v[4:5], v[2:3], 30
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; GCN-NEXT: v_lshrrev_b32_e32 v0, 2, v1
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; GCN-NEXT: v_bfe_u32 v6, v3, 2, 2
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; GCN-NEXT: v_or_b32_e32 v4, v0, v4
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; GCN-NEXT: buffer_store_dwordx4 v[4:7], v[8:9], s[0:3], 0 addr64
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; GCN-NEXT: s_endpgm
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%id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%in.gep = getelementptr i128, i128 addrspace(1)* %in, i32 %id.x
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%out.gep = getelementptr i128, i128 addrspace(1)* %out, i32 %id.x
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%ld.64 = load i128, i128 addrspace(1)* %in.gep
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%srl = lshr i128 %ld.64, 34
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%bit = and i128 %srl, 73786976294838206463
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store i128 %bit, i128 addrspace(1)* %out.gep
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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declare i32 @llvm.amdgcn.workgroup.id.x() #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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