718aec209c
On GFX10.3 targets, the following instruction sequence v_cmp_* SGPR, ... s_and_saveexec ..., SGPR leads to a fairly long stall caused by a VALU write to a SGPR and having the following SALU wait for the SGPR. An equivalent sequence is to save the exec mask manually instead of letting s_and_saveexec do the work and use a v_cmpx instruction instead to do the comparison. This patch modifies the SIOptimizeExecMasking pass as this is the last position where s_and_saveexec instructions are inserted. It does the transformation by trying to find the pattern, extracting the operands and generating the new instruction sequence. It also changes some existing lit tests and introduces a few new tests to show the changed behavior on GFX10.3 targets. Same as D119696 including a buildbot and MIR test fix. Reviewed By: critson Differential Revision: https://reviews.llvm.org/D122332
168 lines
4.3 KiB
LLVM
168 lines
4.3 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX1010 %s
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; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX1030 %s
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; GCN-LABEL: {{^}}test_insert_vcmpx_pattern_lt:
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; GFX1010: v_cmp_lt_i32_e32 vcc_lo, 15, v{{.*}}
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; GFX1010-NEXT: s_and_saveexec_b32 s{{.*}}, vcc_lo
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; GFX1030: s_mov_b32 s{{.*}}, exec_lo
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; GFX1030-NEXT: v_cmpx_lt_i32_e32 15, v{{.*}}
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define i32 @test_insert_vcmpx_pattern_lt(i32 %x) {
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entry:
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%bc = icmp slt i32 %x, 16
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br i1 %bc, label %endif, label %if
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if:
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%ret = shl i32 %x, 2
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ret i32 %ret
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endif:
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ret i32 %x
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}
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; GCN-LABEL: {{^}}test_insert_vcmpx_pattern_gt:
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; GFX1010: v_cmp_gt_i32_e32 vcc_lo, 17, v{{.*}}
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; GFX1010-NEXT: s_and_saveexec_b32 s{{.*}}, vcc_lo
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; GFX1030: s_mov_b32 s{{.*}}, exec_lo
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; GFX1030-NEXT: v_cmpx_gt_i32_e32 17, v{{.*}}
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define i32 @test_insert_vcmpx_pattern_gt(i32 %x) {
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entry:
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%bc = icmp sgt i32 %x, 16
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br i1 %bc, label %endif, label %if
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if:
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%ret = shl i32 %x, 2
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ret i32 %ret
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endif:
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ret i32 %x
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}
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; GCN-LABEL: {{^}}test_insert_vcmpx_pattern_eq:
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; GFX1010: v_cmp_ne_u32_e32 vcc_lo, 16, v{{.*}}
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; GFX1010-NEXT: s_and_saveexec_b32 s{{.*}}, vcc_lo
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; GFX1030: s_mov_b32 s{{.*}}, exec_lo
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; GFX1030-NEXT: v_cmpx_ne_u32_e32 16, v{{.*}}
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define i32 @test_insert_vcmpx_pattern_eq(i32 %x) {
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entry:
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%bc = icmp eq i32 %x, 16
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br i1 %bc, label %endif, label %if
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if:
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%ret = shl i32 %x, 2
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ret i32 %ret
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endif:
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ret i32 %x
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}
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; GCN-LABEL: {{^}}test_insert_vcmpx_pattern_ne:
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; GFX1010: v_cmp_eq_u32_e32 vcc_lo, 16, v{{.*}}
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; GFX1010-NEXT: s_and_saveexec_b32 s{{.*}}, vcc_lo
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; GFX1030: s_mov_b32 s{{.*}}, exec_lo
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; GFX1030-NEXT: v_cmpx_eq_u32_e32 16, v{{.*}}
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define i32 @test_insert_vcmpx_pattern_ne(i32 %x) {
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entry:
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%bc = icmp ne i32 %x, 16
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br i1 %bc, label %endif, label %if
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if:
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%ret = shl i32 %x, 2
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ret i32 %ret
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endif:
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ret i32 %x
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}
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; GCN-LABEL: {{^}}test_insert_vcmpx_pattern_le:
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; GFX1010: v_cmp_lt_i32_e32 vcc_lo, 16, v{{.*}}
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; GFX1010-NEXT: s_and_saveexec_b32 s{{.*}}, vcc_lo
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; GFX1030: s_mov_b32 s{{.*}}, exec_lo
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; GFX1030-NEXT: v_cmpx_lt_i32_e32 16, v{{.*}}
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define i32 @test_insert_vcmpx_pattern_le(i32 %x) {
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entry:
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%bc = icmp sle i32 %x, 16
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br i1 %bc, label %endif, label %if
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if:
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%ret = shl i32 %x, 2
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ret i32 %ret
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endif:
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ret i32 %x
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}
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; GCN-LABEL: {{^}}test_insert_vcmpx_pattern_ge:
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; GFX1010: v_cmp_gt_i32_e32 vcc_lo, 16, v{{.*}}
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; GFX1010-NEXT: s_and_saveexec_b32 s{{.*}}, vcc_lo
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; GFX1030: s_mov_b32 s{{.*}}, exec_lo
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; GFX1030-NEXT: v_cmpx_gt_i32_e32 16, v{{.*}}
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define i32 @test_insert_vcmpx_pattern_ge(i32 %x) {
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entry:
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%bc = icmp sge i32 %x, 16
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br i1 %bc, label %endif, label %if
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if:
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%ret = shl i32 %x, 2
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ret i32 %ret
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endif:
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ret i32 %x
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}
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declare amdgpu_gfx void @check_live_outs_helper(i64) #0
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; In cases where the output operand cannot be safely removed,
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; don't apply the v_cmpx transformation.
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; GCN-LABEL: {{^}}check_live_outs:
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; GFX1010: v_cmp_eq_u32_e64 s{{.*}}, v{{.*}}, v{{.*}}
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; GFX1010: s_and_saveexec_b32 s{{.*}}, s{{.*}}
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; GFX1030: v_cmp_eq_u32_e64 s{{.*}}, v{{.*}}, v{{.*}}
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; GFX1030: s_and_saveexec_b32 s{{.*}}, s{{.*}}
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define amdgpu_cs void @check_live_outs(i32 %a, i32 %b) {
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%cond = icmp eq i32 %a, %b
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%result = call i64 @llvm.amdgcn.icmp.i32(i32 %a, i32 %b, i32 32)
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br i1 %cond, label %l1, label %l2
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l1:
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call amdgpu_gfx void @check_live_outs_helper(i64 %result)
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br label %l2
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l2:
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ret void
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}
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; Omit the transformation if the s_and_saveexec instruction overwrites
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; any of the v_cmp source operands.
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; GCN-LABEL: check_saveexec_overwrites_vcmp_source:
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; GCN: ; %bb.1: ; %then
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; GFX1010: v_cmp_ge_i32_e32 vcc_lo, s[[A:[0-9]+]], v{{.*}}
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; GFX1010-NEXT: v_mov_b32_e32 {{.*}}, s[[A]]
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; GFX1010-NEXT: s_and_saveexec_b32 s[[A]], vcc_lo
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; GFX1030: v_cmp_ge_i32_e32 vcc_lo, s[[A:[0-9]+]], v{{.*}}
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; GFX1030-NEXT: v_mov_b32_e32 {{.*}}, s[[A]]
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; GFX1030-NEXT: s_and_saveexec_b32 s[[A]], vcc_lo
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define i32 @check_saveexec_overwrites_vcmp_source(i32 inreg %a, i32 inreg %b) {
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entry:
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%0 = icmp sge i32 %a, 0
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br i1 %0, label %if, label %then
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if:
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%1 = shl i32 %a, 2
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%2 = or i32 %1, %b
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ret i32 %2
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then:
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%3 = call i64 @llvm.amdgcn.icmp.i32(i32 %a, i32 %b, i32 32)
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%4 = trunc i64 %3 to i32
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%5 = icmp slt i32 %4, %b
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br i1 %5, label %after, label %end
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after:
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ret i32 %4
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end:
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ret i32 %a
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}
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declare i64 @llvm.amdgcn.icmp.i32(i32, i32, i32) #0
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