fae05692a3
This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
616 lines
16 KiB
YAML
616 lines
16 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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define void @test_trunc_and_zext_s1_to_s32() { ret void }
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define void @test_trunc_and_sext_s1_to_s32() { ret void }
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define void @test_trunc_and_anyext_s1_to_s32() { ret void }
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define void @test_trunc_and_zext_s8_to_s32() { ret void }
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define void @test_trunc_and_sext_s8_to_s32() { ret void }
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define void @test_trunc_and_anyext_s8_to_s32() { ret void }
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define void @test_trunc_and_zext_s16_to_s32() { ret void }
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define void @test_trunc_and_sext_s16_to_s32() { ret void }
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define void @test_trunc_and_anyext_s16_to_s32() { ret void }
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define void @test_trunc_and_zext_s1_to_s16() { ret void }
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define void @test_trunc_and_sext_s1_to_s16() { ret void }
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define void @test_trunc_and_anyext_s1_to_s16() { ret void }
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define void @test_trunc_and_zext_s8_to_s16() { ret void }
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define void @test_trunc_and_sext_s8_to_s16() { ret void }
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define void @test_trunc_and_anyext_s8_to_s16() { ret void }
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define void @test_trunc_and_zext_s1_to_s8() { ret void }
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define void @test_trunc_and_sext_s1_to_s8() { ret void }
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define void @test_trunc_and_anyext_s1_to_s8() { ret void }
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...
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---
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name: test_trunc_and_zext_s1_to_s32
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s32
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; CHECK: liveins: $r0
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; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
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; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ANDri]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s1) = G_TRUNC %0(s32)
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%2(s32) = G_ZEXT %1(s1)
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$r0 = COPY %2(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_sext_s1_to_s32
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s32
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; CHECK: liveins: $r0
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; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
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; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[t2ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2RSBri]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s1) = G_TRUNC %0(s32)
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%2(s32) = G_SEXT %1(s1)
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$r0 = COPY %2(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_anyext_s1_to_s32
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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; CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s32
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; CHECK: liveins: $r0
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; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
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; CHECK: $r0 = COPY [[COPY]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s1) = G_TRUNC %0(s32)
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%2(s32) = G_ANYEXT %1(s1)
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$r0 = COPY %2(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_zext_s8_to_s32
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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; CHECK-LABEL: name: test_trunc_and_zext_s8_to_s32
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; CHECK: liveins: $r0
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; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
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; CHECK: [[t2UXTB:%[0-9]+]]:rgpr = t2UXTB [[COPY1]], 0, 14 /* CC::al */, $noreg
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; CHECK: $r0 = COPY [[t2UXTB]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s8) = G_TRUNC %0(s32)
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%2(s32) = G_ZEXT %1(s8)
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$r0 = COPY %2(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_sext_s8_to_s32
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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; CHECK-LABEL: name: test_trunc_and_sext_s8_to_s32
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; CHECK: liveins: $r0
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; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
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; CHECK: [[t2SXTB:%[0-9]+]]:rgpr = t2SXTB [[COPY1]], 0, 14 /* CC::al */, $noreg
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; CHECK: $r0 = COPY [[t2SXTB]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s8) = G_TRUNC %0(s32)
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%2(s32) = G_SEXT %1(s8)
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$r0 = COPY %2(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_anyext_s8_to_s32
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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; CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s32
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; CHECK: liveins: $r0
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; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
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; CHECK: $r0 = COPY [[COPY]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s8) = G_TRUNC %0(s32)
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%2(s32) = G_ANYEXT %1(s8)
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$r0 = COPY %2(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_zext_s16_to_s32
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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; CHECK-LABEL: name: test_trunc_and_zext_s16_to_s32
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; CHECK: liveins: $r0
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; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
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; CHECK: [[t2UXTH:%[0-9]+]]:rgpr = t2UXTH [[COPY1]], 0, 14 /* CC::al */, $noreg
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; CHECK: $r0 = COPY [[t2UXTH]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s16) = G_TRUNC %0(s32)
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%2(s32) = G_ZEXT %1(s16)
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$r0 = COPY %2(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_sext_s16_to_s32
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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; CHECK-LABEL: name: test_trunc_and_sext_s16_to_s32
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; CHECK: liveins: $r0
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; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
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; CHECK: [[t2SXTH:%[0-9]+]]:rgpr = t2SXTH [[COPY1]], 0, 14 /* CC::al */, $noreg
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; CHECK: $r0 = COPY [[t2SXTH]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s16) = G_TRUNC %0(s32)
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%2(s32) = G_SEXT %1(s16)
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$r0 = COPY %2(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_anyext_s16_to_s32
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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; CHECK-LABEL: name: test_trunc_and_anyext_s16_to_s32
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; CHECK: liveins: $r0
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; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
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; CHECK: $r0 = COPY [[COPY]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s16) = G_TRUNC %0(s32)
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%2(s32) = G_ANYEXT %1(s16)
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$r0 = COPY %2(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_zext_s1_to_s16
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s16
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; CHECK: liveins: $r0, $r1
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; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
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; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
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; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY2]], 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: t2STRHi12 [[t2ANDri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s16))
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; CHECK: BX_RET 14 /* CC::al */, $noreg
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%0(p0) = COPY $r0
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%1(s32) = COPY $r1
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%2(s1) = G_TRUNC %1(s32)
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%3(s16) = G_ZEXT %2(s1)
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G_STORE %3(s16), %0(p0) :: (store (s16))
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BX_RET 14, $noreg
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...
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---
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name: test_trunc_and_sext_s1_to_s16
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s16
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; CHECK: liveins: $r0, $r1
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; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
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; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
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; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY2]], 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[t2ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
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; CHECK: t2STRHi12 [[t2RSBri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s16))
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; CHECK: BX_RET 14 /* CC::al */, $noreg
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%0(p0) = COPY $r0
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%1(s32) = COPY $r1
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%2(s1) = G_TRUNC %1(s32)
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%3(s16) = G_SEXT %2(s1)
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G_STORE %3(s16), %0(p0) :: (store (s16))
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BX_RET 14, $noreg
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...
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---
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name: test_trunc_and_anyext_s1_to_s16
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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; CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s16
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; CHECK: liveins: $r0, $r1
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; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
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; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
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; CHECK: t2STRHi12 [[COPY2]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s16))
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; CHECK: BX_RET 14 /* CC::al */, $noreg
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%0(p0) = COPY $r0
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%1(s32) = COPY $r1
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%2(s1) = G_TRUNC %1(s32)
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%3(s16) = G_ANYEXT %2(s1)
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G_STORE %3(s16), %0(p0) :: (store (s16))
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BX_RET 14, $noreg
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...
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---
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name: test_trunc_and_zext_s8_to_s16
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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; CHECK-LABEL: name: test_trunc_and_zext_s8_to_s16
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; CHECK: liveins: $r0, $r1
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; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
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; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
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; CHECK: [[t2UXTB:%[0-9]+]]:rgpr = t2UXTB [[COPY2]], 0, 14 /* CC::al */, $noreg
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; CHECK: t2STRHi12 [[t2UXTB]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s16))
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; CHECK: BX_RET 14 /* CC::al */, $noreg
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%0(p0) = COPY $r0
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%1(s32) = COPY $r1
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%2(s8) = G_TRUNC %1(s32)
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|
|
%3(s16) = G_ZEXT %2(s8)
|
|
|
|
G_STORE %3(s16), %0(p0) :: (store (s16))
|
|
|
|
BX_RET 14, $noreg
|
|
...
|
|
---
|
|
name: test_trunc_and_sext_s8_to_s16
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: gprb }
|
|
- { id: 2, class: gprb }
|
|
- { id: 3, class: gprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0, $r1
|
|
|
|
; CHECK-LABEL: name: test_trunc_and_sext_s8_to_s16
|
|
; CHECK: liveins: $r0, $r1
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
|
|
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
|
|
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
|
|
; CHECK: [[t2SXTB:%[0-9]+]]:rgpr = t2SXTB [[COPY2]], 0, 14 /* CC::al */, $noreg
|
|
; CHECK: t2STRHi12 [[t2SXTB]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s16))
|
|
; CHECK: BX_RET 14 /* CC::al */, $noreg
|
|
%0(p0) = COPY $r0
|
|
|
|
%1(s32) = COPY $r1
|
|
|
|
%2(s8) = G_TRUNC %1(s32)
|
|
|
|
%3(s16) = G_SEXT %2(s8)
|
|
|
|
G_STORE %3(s16), %0(p0) :: (store (s16))
|
|
|
|
BX_RET 14, $noreg
|
|
...
|
|
---
|
|
name: test_trunc_and_anyext_s8_to_s16
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: gprb }
|
|
- { id: 2, class: gprb }
|
|
- { id: 3, class: gprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0, $r1
|
|
|
|
; CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s16
|
|
; CHECK: liveins: $r0, $r1
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
|
|
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
|
|
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
|
|
; CHECK: t2STRHi12 [[COPY2]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s16))
|
|
; CHECK: BX_RET 14 /* CC::al */, $noreg
|
|
%0(p0) = COPY $r0
|
|
|
|
%1(s32) = COPY $r1
|
|
|
|
%2(s8) = G_TRUNC %1(s32)
|
|
|
|
%3(s16) = G_ANYEXT %2(s8)
|
|
|
|
G_STORE %3(s16), %0(p0) :: (store (s16))
|
|
|
|
BX_RET 14, $noreg
|
|
...
|
|
---
|
|
name: test_trunc_and_zext_s1_to_s8
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: gprb }
|
|
- { id: 2, class: gprb }
|
|
- { id: 3, class: gprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0, $r1
|
|
|
|
; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s8
|
|
; CHECK: liveins: $r0, $r1
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
|
|
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
|
|
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
|
|
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY2]], 1, 14 /* CC::al */, $noreg, $noreg
|
|
; CHECK: t2STRBi12 [[t2ANDri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s8))
|
|
; CHECK: BX_RET 14 /* CC::al */, $noreg
|
|
%0(p0) = COPY $r0
|
|
|
|
%1(s32) = COPY $r1
|
|
|
|
%2(s1) = G_TRUNC %1(s32)
|
|
|
|
%3(s8) = G_ZEXT %2(s1)
|
|
|
|
G_STORE %3(s8), %0(p0) :: (store (s8))
|
|
|
|
BX_RET 14, $noreg
|
|
...
|
|
---
|
|
name: test_trunc_and_sext_s1_to_s8
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: gprb }
|
|
- { id: 2, class: gprb }
|
|
- { id: 3, class: gprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0, $r1
|
|
|
|
; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s8
|
|
; CHECK: liveins: $r0, $r1
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
|
|
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
|
|
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
|
|
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY2]], 1, 14 /* CC::al */, $noreg, $noreg
|
|
; CHECK: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[t2ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
|
|
; CHECK: t2STRBi12 [[t2RSBri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s8))
|
|
; CHECK: BX_RET 14 /* CC::al */, $noreg
|
|
%0(p0) = COPY $r0
|
|
|
|
%1(s32) = COPY $r1
|
|
|
|
%2(s1) = G_TRUNC %1(s32)
|
|
|
|
%3(s8) = G_SEXT %2(s1)
|
|
|
|
G_STORE %3(s8), %0(p0) :: (store (s8))
|
|
|
|
BX_RET 14, $noreg
|
|
...
|
|
---
|
|
name: test_trunc_and_anyext_s1_to_s8
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: gprb }
|
|
- { id: 2, class: gprb }
|
|
- { id: 3, class: gprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0, $r1
|
|
|
|
; CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s8
|
|
; CHECK: liveins: $r0, $r1
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
|
|
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
|
|
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
|
|
; CHECK: t2STRBi12 [[COPY2]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s8))
|
|
; CHECK: BX_RET 14 /* CC::al */, $noreg
|
|
%0(p0) = COPY $r0
|
|
|
|
%1(s32) = COPY $r1
|
|
|
|
%2(s1) = G_TRUNC %1(s32)
|
|
|
|
%3(s8) = G_ANYEXT %2(s1)
|
|
|
|
G_STORE %3(s8), %0(p0) :: (store (s8))
|
|
|
|
BX_RET 14, $noreg
|
|
...
|