b1d47467e2
This commit removes the artificial types <512 x i1> and <1024 x i1>
from HVX intrinsics, and makes v512i1 and v1024i1 no longer legal on
Hexagon.
It may cause existing bitcode files to become invalid.
* Converting between vector predicates and vector registers must be
done explicitly via vandvrt/vandqrt instructions (their intrinsics),
i.e. (for 64-byte mode):
%Q = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %V, i32 -1)
%V = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %Q, i32 -1)
The conversion intrinsics are:
declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32)
declare <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32>, i32)
declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32)
declare <32 x i32> @llvm.hexagon.V6.vandqrt.128B(<128 x i1>, i32)
They are all pure.
* Vector predicate values cannot be loaded/stored directly. This directly
reflects the architecture restriction. Loading and storing or vector
predicates must be done indirectly via vector registers and explicit
conversions via vandvrt/vandqrt instructions.
96 lines
2.9 KiB
LLVM
96 lines
2.9 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK-LABEL: t00
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; CHECK: vand(v{{[0-9:]+}},v{{[0-9:]+}})
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define <128 x i8> @t00(<128 x i8> %a0, <128 x i8> %a1) #0 {
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%q0 = trunc <128 x i8> %a0 to <128 x i1>
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%q1 = trunc <128 x i8> %a1 to <128 x i1>
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%q2 = and <128 x i1> %q0, %q1
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%v0 = zext <128 x i1> %q2 to <128 x i8>
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ret <128 x i8> %v0
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}
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declare <128 x i1> @llvm.hexagon.vandvrt.128B(<128 x i8>, i32)
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; CHECK-LABEL: t01
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; CHECK: vor(v{{[0-9:]+}},v{{[0-9:]+}})
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define <128 x i8> @t01(<128 x i8> %a0, <128 x i8> %a1) #0 {
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%q0 = trunc <128 x i8> %a0 to <128 x i1>
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%q1 = trunc <128 x i8> %a1 to <128 x i1>
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%q2 = or <128 x i1> %q0, %q1
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%v0 = zext <128 x i1> %q2 to <128 x i8>
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ret <128 x i8> %v0
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}
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; CHECK-LABEL: t02
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; CHECK: vxor(v{{[0-9:]+}},v{{[0-9:]+}})
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define <128 x i8> @t02(<128 x i8> %a0, <128 x i8> %a1) #0 {
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%q0 = trunc <128 x i8> %a0 to <128 x i1>
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%q1 = trunc <128 x i8> %a1 to <128 x i1>
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%q2 = xor <128 x i1> %q0, %q1
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%v0 = zext <128 x i1> %q2 to <128 x i8>
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ret <128 x i8> %v0
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}
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; CHECK-LABEL: t10
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; CHECK: vand(v{{[0-9:]+}},v{{[0-9:]+}})
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define <64 x i16> @t10(<64 x i16> %a0, <64 x i16> %a1) #0 {
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%q0 = trunc <64 x i16> %a0 to <64 x i1>
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%q1 = trunc <64 x i16> %a1 to <64 x i1>
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%q2 = and <64 x i1> %q0, %q1
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%v0 = zext <64 x i1> %q2 to <64 x i16>
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ret <64 x i16> %v0
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}
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; CHECK-LABEL: t11
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; CHECK: vor(v{{[0-9:]+}},v{{[0-9:]+}})
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define <64 x i16> @t11(<64 x i16> %a0, <64 x i16> %a1) #0 {
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%q0 = trunc <64 x i16> %a0 to <64 x i1>
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%q1 = trunc <64 x i16> %a1 to <64 x i1>
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%q2 = or <64 x i1> %q0, %q1
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%v0 = zext <64 x i1> %q2 to <64 x i16>
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ret <64 x i16> %v0
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}
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; CHECK-LABEL: t12
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; CHECK: vxor(v{{[0-9:]+}},v{{[0-9:]+}})
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define <64 x i16> @t12(<64 x i16> %a0, <64 x i16> %a1) #0 {
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%q0 = trunc <64 x i16> %a0 to <64 x i1>
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%q1 = trunc <64 x i16> %a1 to <64 x i1>
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%q2 = xor <64 x i1> %q0, %q1
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%v0 = zext <64 x i1> %q2 to <64 x i16>
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ret <64 x i16> %v0
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}
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; CHECK-LABEL: t20
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; CHECK: vand(v{{[0-9:]+}},v{{[0-9:]+}})
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define <32 x i32> @t20(<32 x i32> %a0, <32 x i32> %a1) #0 {
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%q0 = trunc <32 x i32> %a0 to <32 x i1>
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%q1 = trunc <32 x i32> %a1 to <32 x i1>
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%q2 = and <32 x i1> %q0, %q1
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%v0 = zext <32 x i1> %q2 to <32 x i32>
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ret <32 x i32> %v0
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}
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; CHECK-LABEL: t21
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; CHECK: vor(v{{[0-9:]+}},v{{[0-9:]+}})
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define <32 x i32> @t21(<32 x i32> %a0, <32 x i32> %a1) #0 {
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%q0 = trunc <32 x i32> %a0 to <32 x i1>
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%q1 = trunc <32 x i32> %a1 to <32 x i1>
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%q2 = or <32 x i1> %q0, %q1
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%v0 = zext <32 x i1> %q2 to <32 x i32>
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ret <32 x i32> %v0
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}
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; CHECK-LABEL: t22
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; CHECK: vxor(v{{[0-9:]+}},v{{[0-9:]+}})
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define <32 x i32> @t22(<32 x i32> %a0, <32 x i32> %a1) #0 {
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%q0 = trunc <32 x i32> %a0 to <32 x i1>
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%q1 = trunc <32 x i32> %a1 to <32 x i1>
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%q2 = xor <32 x i1> %q0, %q1
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%v0 = zext <32 x i1> %q2 to <32 x i32>
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ret <32 x i32> %v0
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}
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attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
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