657bb7262d
Previously ADD & ADDA (as well as SUB & SUBA) instructions are mixed together, which not only violated Motorola assembly's syntax but also made asm parsing more difficult. This patch separates these two kinds of instructions migrate rest of the tests from test/CodeGen/M68k/Encoding/Arithmetic to test/MC/M68k/Arithmetic. Note that we observed minor regressions on codegen quality: Sometimes isel uses ADD instead of ADDA even the latter can lead to shorter sequence of code. This issue implies that some isel patterns might need to be updated.
215 lines
5.7 KiB
LLVM
215 lines
5.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s
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; TODO fold the shifts
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define zeroext i16 @test1(i16 zeroext %x) nounwind {
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; CHECK-LABEL: test1:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: move.w (6,%sp), %d0
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; CHECK-NEXT: mulu #-1985, %d0
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; CHECK-NEXT: lsr.l #8, %d0
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; CHECK-NEXT: lsr.l #8, %d0
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; CHECK-NEXT: lsr.w #5, %d0
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; CHECK-NEXT: and.l #65535, %d0
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; CHECK-NEXT: rts
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entry:
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%div = udiv i16 %x, 33
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ret i16 %div
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}
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define zeroext i16 @test2(i8 signext %x, i16 zeroext %c) {
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; CHECK-LABEL: test2:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0: ; %entry
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; CHECK-NEXT: move.w (10,%sp), %d0
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; CHECK-NEXT: mulu #-21845, %d0
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; CHECK-NEXT: lsr.l #8, %d0
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; CHECK-NEXT: lsr.l #8, %d0
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; CHECK-NEXT: lsr.w #1, %d0
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; CHECK-NEXT: and.l #65535, %d0
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; CHECK-NEXT: rts
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entry:
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%div = udiv i16 %c, 3
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ret i16 %div
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}
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define zeroext i8 @test3(i8 zeroext %x, i8 zeroext %c) {
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; CHECK-LABEL: test3:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0: ; %entry
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; CHECK-NEXT: move.b (11,%sp), %d0
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; CHECK-NEXT: and.l #255, %d0
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; CHECK-NEXT: mulu #-21845, %d0
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; CHECK-NEXT: lsr.l #8, %d0
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; CHECK-NEXT: lsr.l #8, %d0
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; CHECK-NEXT: lsr.w #1, %d0
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; CHECK-NEXT: and.l #65535, %d0
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; CHECK-NEXT: rts
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entry:
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%div = udiv i8 %c, 3
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ret i8 %div
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}
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define signext i16 @test4(i16 signext %x) nounwind {
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; CHECK-LABEL: test4:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: suba.l #4, %sp
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; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
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; CHECK-NEXT: move.w (10,%sp), %d0
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; CHECK-NEXT: muls #1986, %d0
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; CHECK-NEXT: asr.l #8, %d0
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; CHECK-NEXT: asr.l #8, %d0
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; CHECK-NEXT: move.w #15, %d1
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; CHECK-NEXT: move.w %d0, %d2
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; CHECK-NEXT: lsr.w %d1, %d2
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; CHECK-NEXT: add.w %d2, %d0
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; CHECK-NEXT: ext.l %d0
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; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
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; CHECK-NEXT: adda.l #4, %sp
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; CHECK-NEXT: rts
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entry:
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%div = sdiv i16 %x, 33 ; <i32> [#uses=1]
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ret i16 %div
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}
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define i32 @test5(i32 %A) nounwind {
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; CHECK-LABEL: test5:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: suba.l #12, %sp
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; CHECK-NEXT: move.l #1577682821, (4,%sp)
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; CHECK-NEXT: move.l (16,%sp), (%sp)
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; CHECK-NEXT: jsr __udivsi3@PLT
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; CHECK-NEXT: adda.l #12, %sp
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; CHECK-NEXT: rts
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%tmp1 = udiv i32 %A, 1577682821 ; <i32> [#uses=1]
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ret i32 %tmp1
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}
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; TODO fold shift
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define signext i16 @test6(i16 signext %x) nounwind {
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; CHECK-LABEL: test6:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: suba.l #4, %sp
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; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
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; CHECK-NEXT: move.w (10,%sp), %d0
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; CHECK-NEXT: muls #26215, %d0
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; CHECK-NEXT: asr.l #8, %d0
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; CHECK-NEXT: asr.l #8, %d0
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; CHECK-NEXT: move.w #15, %d1
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; CHECK-NEXT: move.w %d0, %d2
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; CHECK-NEXT: lsr.w %d1, %d2
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; CHECK-NEXT: asr.w #2, %d0
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; CHECK-NEXT: add.w %d2, %d0
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; CHECK-NEXT: ext.l %d0
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; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
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; CHECK-NEXT: adda.l #4, %sp
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; CHECK-NEXT: rts
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entry:
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%div = sdiv i16 %x, 10
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ret i16 %div
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}
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define i32 @test7(i32 %x) nounwind {
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; CHECK-LABEL: test7:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: suba.l #12, %sp
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; CHECK-NEXT: move.l #28, (4,%sp)
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; CHECK-NEXT: move.l (16,%sp), (%sp)
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; CHECK-NEXT: jsr __udivsi3@PLT
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; CHECK-NEXT: adda.l #12, %sp
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; CHECK-NEXT: rts
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%div = udiv i32 %x, 28
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ret i32 %div
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}
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define i8 @test8(i8 %x) nounwind {
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; CHECK-LABEL: test8:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.b (7,%sp), %d0
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; CHECK-NEXT: and.l #255, %d0
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; CHECK-NEXT: lsr.w #1, %d0
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; CHECK-NEXT: mulu #26887, %d0
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; CHECK-NEXT: lsr.l #8, %d0
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; CHECK-NEXT: lsr.l #8, %d0
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; CHECK-NEXT: lsr.w #4, %d0
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; CHECK-NEXT: ; kill: def $bd0 killed $bd0 killed $d0
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; CHECK-NEXT: rts
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%div = udiv i8 %x, 78
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ret i8 %div
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}
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define i8 @test9(i8 %x) nounwind {
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; CHECK-LABEL: test9:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.b (7,%sp), %d0
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; CHECK-NEXT: and.l #255, %d0
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; CHECK-NEXT: mulu #18079, %d0
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; CHECK-NEXT: lsr.l #8, %d0
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; CHECK-NEXT: lsr.l #8, %d0
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; CHECK-NEXT: lsr.w #5, %d0
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; CHECK-NEXT: ; kill: def $bd0 killed $bd0 killed $d0
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; CHECK-NEXT: rts
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%div = udiv i8 %x, 116
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ret i8 %div
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}
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define i32 @testsize1(i32 %x) minsize nounwind {
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; CHECK-LABEL: testsize1:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: suba.l #4, %sp
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; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
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; CHECK-NEXT: move.l #31, %d1
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; CHECK-NEXT: move.l (8,%sp), %d0
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; CHECK-NEXT: move.l %d0, %d2
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; CHECK-NEXT: asr.l %d1, %d2
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; CHECK-NEXT: move.l #27, %d1
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; CHECK-NEXT: lsr.l %d1, %d2
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; CHECK-NEXT: add.l %d2, %d0
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; CHECK-NEXT: asr.l #5, %d0
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; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
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; CHECK-NEXT: adda.l #4, %sp
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; CHECK-NEXT: rts
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entry:
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%div = sdiv i32 %x, 32
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ret i32 %div
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}
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define i32 @testsize2(i32 %x) minsize nounwind {
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; CHECK-LABEL: testsize2:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: suba.l #12, %sp
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; CHECK-NEXT: move.l #33, (4,%sp)
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; CHECK-NEXT: move.l (16,%sp), (%sp)
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; CHECK-NEXT: jsr __divsi3@PLT
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; CHECK-NEXT: adda.l #12, %sp
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; CHECK-NEXT: rts
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entry:
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%div = sdiv i32 %x, 33
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ret i32 %div
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}
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define i32 @testsize3(i32 %x) minsize nounwind {
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; CHECK-LABEL: testsize3:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: move.l (4,%sp), %d0
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; CHECK-NEXT: lsr.l #5, %d0
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; CHECK-NEXT: rts
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entry:
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%div = udiv i32 %x, 32
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ret i32 %div
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}
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define i32 @testsize4(i32 %x) minsize nounwind {
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; CHECK-LABEL: testsize4:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: suba.l #12, %sp
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; CHECK-NEXT: move.l #33, (4,%sp)
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; CHECK-NEXT: move.l (16,%sp), (%sp)
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; CHECK-NEXT: jsr __udivsi3@PLT
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; CHECK-NEXT: adda.l #12, %sp
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; CHECK-NEXT: rts
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entry:
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%div = udiv i32 %x, 33
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ret i32 %div
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}
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