657bb7262d
Previously ADD & ADDA (as well as SUB & SUBA) instructions are mixed together, which not only violated Motorola assembly's syntax but also made asm parsing more difficult. This patch separates these two kinds of instructions migrate rest of the tests from test/CodeGen/M68k/Encoding/Arithmetic to test/MC/M68k/Arithmetic. Note that we observed minor regressions on codegen quality: Sometimes isel uses ADD instead of ADDA even the latter can lead to shorter sequence of code. This issue implies that some isel patterns might need to be updated.
35 lines
1022 B
LLVM
35 lines
1022 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=m68k-linux -verify-machineinstrs < %s | FileCheck %s
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define i32 @test1(i32 %x) {
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; CHECK-LABEL: test1:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: suba.l #12, %sp
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; CHECK-NEXT: .cfi_def_cfa_offset -16
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; CHECK-NEXT: move.l #-1030792151, (4,%sp)
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; CHECK-NEXT: move.l (16,%sp), (%sp)
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; CHECK-NEXT: jsr __mulsi3@PLT
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; CHECK-NEXT: adda.l #12, %sp
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; CHECK-NEXT: rts
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%div = sdiv exact i32 %x, 25
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ret i32 %div
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}
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define i32 @test2(i32 %x) {
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; CHECK-LABEL: test2:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: suba.l #12, %sp
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; CHECK-NEXT: .cfi_def_cfa_offset -16
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; CHECK-NEXT: move.l (16,%sp), %d0
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; CHECK-NEXT: asr.l #3, %d0
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; CHECK-NEXT: move.l %d0, (%sp)
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; CHECK-NEXT: move.l #-1431655765, (4,%sp)
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; CHECK-NEXT: jsr __mulsi3@PLT
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; CHECK-NEXT: adda.l #12, %sp
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; CHECK-NEXT: rts
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%div = sdiv exact i32 %x, 24
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ret i32 %div
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}
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