657bb7262d
Previously ADD & ADDA (as well as SUB & SUBA) instructions are mixed together, which not only violated Motorola assembly's syntax but also made asm parsing more difficult. This patch separates these two kinds of instructions migrate rest of the tests from test/CodeGen/M68k/Encoding/Arithmetic to test/MC/M68k/Arithmetic. Note that we observed minor regressions on codegen quality: Sometimes isel uses ADD instead of ADDA even the latter can lead to shorter sequence of code. This issue implies that some isel patterns might need to be updated.
97 lines
3.1 KiB
LLVM
97 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s
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declare i32 @printf(i8*, ...) nounwind
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declare {i32, i1} @llvm.ssub.with.overflow.i32(i32, i32)
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declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32)
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@ok = internal constant [4 x i8] c"%d\0A\00"
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@no = internal constant [4 x i8] c"no\0A\00"
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define i1 @func1(i32 %v1, i32 %v2) nounwind {
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; CHECK-LABEL: func1:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: suba.l #12, %sp
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; CHECK-NEXT: move.l (16,%sp), %d0
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; CHECK-NEXT: sub.l (20,%sp), %d0
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; CHECK-NEXT: bvc .LBB0_1
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; CHECK-NEXT: ; %bb.2: ; %overflow
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; CHECK-NEXT: lea (no,%pc), %a0
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; CHECK-NEXT: move.l %a0, (%sp)
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; CHECK-NEXT: jsr printf@PLT
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; CHECK-NEXT: move.b #0, %d0
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; CHECK-NEXT: adda.l #12, %sp
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; CHECK-NEXT: rts
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; CHECK-NEXT: .LBB0_1: ; %normal
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; CHECK-NEXT: move.l %d0, (4,%sp)
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; CHECK-NEXT: lea (ok,%pc), %a0
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; CHECK-NEXT: move.l %a0, (%sp)
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; CHECK-NEXT: jsr printf@PLT
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; CHECK-NEXT: move.b #1, %d0
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; CHECK-NEXT: adda.l #12, %sp
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; CHECK-NEXT: rts
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entry:
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%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
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%sum = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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br i1 %obit, label %overflow, label %normal
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normal:
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%t1 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
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ret i1 true
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overflow:
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%t2 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @no, i32 0, i32 0) ) nounwind
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ret i1 false
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}
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define i1 @func2(i32 %v1, i32 %v2) nounwind {
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; CHECK-LABEL: func2:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: suba.l #12, %sp
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; CHECK-NEXT: move.l (16,%sp), %d0
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; CHECK-NEXT: sub.l (20,%sp), %d0
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; CHECK-NEXT: bcc .LBB1_1
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; CHECK-NEXT: ; %bb.2: ; %carry
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; CHECK-NEXT: lea (no,%pc), %a0
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; CHECK-NEXT: move.l %a0, (%sp)
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; CHECK-NEXT: jsr printf@PLT
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; CHECK-NEXT: move.b #0, %d0
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; CHECK-NEXT: adda.l #12, %sp
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; CHECK-NEXT: rts
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; CHECK-NEXT: .LBB1_1: ; %normal
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; CHECK-NEXT: move.l %d0, (4,%sp)
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; CHECK-NEXT: lea (ok,%pc), %a0
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; CHECK-NEXT: move.l %a0, (%sp)
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; CHECK-NEXT: jsr printf@PLT
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; CHECK-NEXT: move.b #1, %d0
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; CHECK-NEXT: adda.l #12, %sp
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; CHECK-NEXT: rts
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entry:
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%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
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%sum = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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br i1 %obit, label %carry, label %normal
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normal:
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%t1 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
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ret i1 true
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carry:
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%t2 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @no, i32 0, i32 0) ) nounwind
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ret i1 false
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}
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define i1 @func3(i32 %x) nounwind {
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; CHECK-LABEL: func3:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: move.l #-1, %d0
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; CHECK-NEXT: add.l (4,%sp), %d0
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; CHECK-NEXT: svs %d0
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; CHECK-NEXT: rts
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entry:
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%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %x, i32 1)
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%obit = extractvalue {i32, i1} %t, 1
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ret i1 %obit
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}
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