657bb7262d
Previously ADD & ADDA (as well as SUB & SUBA) instructions are mixed together, which not only violated Motorola assembly's syntax but also made asm parsing more difficult. This patch separates these two kinds of instructions migrate rest of the tests from test/CodeGen/M68k/Encoding/Arithmetic to test/MC/M68k/Arithmetic. Note that we observed minor regressions on codegen quality: Sometimes isel uses ADD instead of ADDA even the latter can lead to shorter sequence of code. This issue implies that some isel patterns might need to be updated.
66 lines
1.9 KiB
LLVM
66 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=m68k-pc-linux -relocation-model=pic -verify-machineinstrs | FileCheck %s
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;
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; Pass all arguments on the stack in reverse order
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define i32 @test1() nounwind {
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; CHECK-LABEL: test1:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: suba.l #20, %sp
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; CHECK-NEXT: move.l #5, (16,%sp)
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; CHECK-NEXT: move.l #4, (12,%sp)
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; CHECK-NEXT: move.l #3, (8,%sp)
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; CHECK-NEXT: move.l #2, (4,%sp)
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; CHECK-NEXT: move.l #1, (%sp)
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; CHECK-NEXT: jsr (test1_callee@PLT,%pc)
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; CHECK-NEXT: move.l #0, %d0
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; CHECK-NEXT: adda.l #20, %sp
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; CHECK-NEXT: rts
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entry:
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call void @test1_callee(i32 1, i32 2, i32 3, i32 4, i32 5) nounwind
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ret i32 0
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}
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declare void @test1_callee(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e);
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define i16 @test2() nounwind {
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; CHECK-LABEL: test2:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: suba.l #20, %sp
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; CHECK-NEXT: move.l #5, (16,%sp)
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; CHECK-NEXT: move.l #4, (12,%sp)
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; CHECK-NEXT: move.l #3, (8,%sp)
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; CHECK-NEXT: move.l #2, (4,%sp)
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; CHECK-NEXT: move.l #1, (%sp)
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; CHECK-NEXT: jsr (test2_callee@PLT,%pc)
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; CHECK-NEXT: move.w #0, %d0
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; CHECK-NEXT: adda.l #20, %sp
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; CHECK-NEXT: rts
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entry:
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call void @test2_callee(i16 1, i16 2, i16 3, i16 4, i16 5) nounwind
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ret i16 0
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}
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declare void @test2_callee(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e);
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define i8 @test3() nounwind {
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; CHECK-LABEL: test3:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: suba.l #20, %sp
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; CHECK-NEXT: move.l #5, (16,%sp)
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; CHECK-NEXT: move.l #4, (12,%sp)
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; CHECK-NEXT: move.l #3, (8,%sp)
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; CHECK-NEXT: move.l #2, (4,%sp)
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; CHECK-NEXT: move.l #1, (%sp)
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; CHECK-NEXT: jsr (test3_callee@PLT,%pc)
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; CHECK-NEXT: move.b #0, %d0
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; CHECK-NEXT: adda.l #20, %sp
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; CHECK-NEXT: rts
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entry:
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call void @test3_callee(i8 1, i8 2, i8 3, i8 4, i8 5) nounwind
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ret i8 0
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}
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declare void @test3_callee(i8 %a, i8 %b, i8 %c, i8 %d, i8 %e);
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