3bffb1cd0e
Replace individual operands GLC, SLC, and DLC with a single cache_policy bitmask operand. This will reduce the number of operands in MIR and I hope the amount of code. These operands are mostly 0 anyway. Additional advantage that parser will accept these flags in any order unlike now. Differential Revision: https://reviews.llvm.org/D96469
88 lines
3.6 KiB
YAML
88 lines
3.6 KiB
YAML
# RUN: llc -march=amdgcn -run-pass none -o - %s | FileCheck %s
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# This test verifies that the MIR parser can parse target index operands.
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--- |
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%struct.foo = type { float, [5 x i32] }
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@float_gv = internal unnamed_addr addrspace(4) constant [5 x float] [float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00], align 4
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define amdgpu_kernel void @float(float addrspace(1)* %out, i32 %index) #0 {
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entry:
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%0 = getelementptr inbounds [5 x float], [5 x float] addrspace(4)* @float_gv, i32 0, i32 %index
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%1 = load float, float addrspace(4)* %0
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store float %1, float addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @float2(float addrspace(1)* %out, i32 %index) #0 {
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entry:
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%0 = getelementptr inbounds [5 x float], [5 x float] addrspace(4)* @float_gv, i32 0, i32 %index
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%1 = load float, float addrspace(4)* %0
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store float %1, float addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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...
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---
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name: float
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liveins:
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- { reg: '$sgpr0_sgpr1' }
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frameInfo:
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maxAlignment: 8
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body: |
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bb.0.entry:
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liveins: $sgpr0_sgpr1
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$sgpr2_sgpr3 = S_GETPC_B64
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; CHECK: $sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start), implicit-def $scc, implicit-def $scc
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$sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start), implicit-def $scc, implicit-def $scc
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$sgpr3 = S_ADDC_U32 $sgpr3, 0, implicit-def $scc, implicit $scc, implicit-def $scc, implicit $scc
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$sgpr4_sgpr5 = S_LSHR_B64 $sgpr2_sgpr3, 32, implicit-def dead $scc
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$sgpr6 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 11, 0
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$sgpr7 = S_ASHR_I32 $sgpr6, 31, implicit-def dead $scc
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$sgpr6_sgpr7 = S_LSHL_B64 $sgpr6_sgpr7, 2, implicit-def dead $scc
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$sgpr2 = S_ADD_U32 $sgpr2, @float_gv, implicit-def $scc
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$sgpr3 = S_ADDC_U32 $sgpr4, 0, implicit-def dead $scc, implicit $scc
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$sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc
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$sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc
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$sgpr2 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0, 0
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$sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 9, 0
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$sgpr7 = S_MOV_B32 61440
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$sgpr6 = S_MOV_B32 -1
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$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec
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BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec
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S_ENDPGM 0
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...
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---
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name: float2
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liveins:
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- { reg: '$sgpr0_sgpr1' }
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frameInfo:
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maxAlignment: 8
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body: |
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bb.0.entry:
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liveins: $sgpr0_sgpr1
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$sgpr2_sgpr3 = S_GETPC_B64
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; CHECK: $sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def $scc, implicit-def $scc
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$sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def $scc, implicit-def $scc
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$sgpr3 = S_ADDC_U32 $sgpr3, 0, implicit-def $scc, implicit $scc, implicit-def $scc, implicit $scc
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$sgpr4_sgpr5 = S_LSHR_B64 $sgpr2_sgpr3, 32, implicit-def dead $scc
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$sgpr6 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 11, 0
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$sgpr7 = S_ASHR_I32 $sgpr6, 31, implicit-def dead $scc
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$sgpr6_sgpr7 = S_LSHL_B64 $sgpr6_sgpr7, 2, implicit-def dead $scc
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$sgpr2 = S_ADD_U32 $sgpr2, @float_gv, implicit-def $scc
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$sgpr3 = S_ADDC_U32 $sgpr4, 0, implicit-def dead $scc, implicit $scc
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$sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc
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$sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc
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$sgpr2 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0, 0
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$sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 9, 0
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$sgpr7 = S_MOV_B32 61440
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$sgpr6 = S_MOV_B32 -1
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$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec
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BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec
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S_ENDPGM 0
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...
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