d391e4fe84
Be more consistent in the naming convention for the various RET instructions to specify in terms of bitwidth. Helps prevent future scheduler model mismatches like those that were only addressed in D44687. Differential Revision: https://reviews.llvm.org/D113302
31 lines
955 B
YAML
31 lines
955 B
YAML
# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
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--- |
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define void @memory_alignment(<8 x float>* %vec) {
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entry:
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%v = load <8 x float>, <8 x float>* %vec
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%v2 = insertelement <8 x float> %v, float 0.0, i32 4
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store <8 x float> %v2, <8 x float>* %vec
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ret void
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}
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...
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---
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name: memory_alignment
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tracksRegLiveness: true
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liveins:
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- { reg: '$rdi' }
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body: |
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bb.0.entry:
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liveins: $rdi
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; CHECK: [[@LINE+1]]:75: expected an integer literal after 'align'
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$xmm0 = MOVAPSrm $rdi, 1, _, 0, _ :: (load (s128) from %ir.vec, align -32)
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$xmm1 = MOVAPSrm $rdi, 1, _, 16, _ :: (load (s128) from %ir.vec + 16, basealign 32)
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$xmm2 = FsFLD0SS
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$xmm1 = MOVSSrr killed $xmm1, killed $xmm2
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MOVAPSmr $rdi, 1, _, 0, _, killed $xmm0 :: (store (s128) into %ir.vec, align 32)
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MOVAPSmr killed $rdi, 1, _, 16, _, killed $xmm1 :: (store (s128) into %ir.vec + 16, basealign 32)
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RET64
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...
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