d391e4fe84
Be more consistent in the naming convention for the various RET instructions to specify in terms of bitwidth. Helps prevent future scheduler model mismatches like those that were only addressed in D44687. Differential Revision: https://reviews.llvm.org/D113302
37 lines
599 B
YAML
37 lines
599 B
YAML
# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
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# This test ensures that the MIR parser parses immediate machine operands.
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--- |
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define i32 @foo() {
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entry:
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ret i32 42
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}
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define i32 @bar() {
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entry:
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ret i32 -11
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}
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...
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---
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# CHECK: name: foo
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name: foo
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body: |
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bb.0.entry:
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; CHECK: $eax = MOV32ri 42
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; CHECK-NEXT: RET64 $eax
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$eax = MOV32ri 42
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RET64 $eax
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...
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---
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# CHECK: name: bar
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name: bar
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body: |
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bb.0.entry:
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; CHECK: $eax = MOV32ri -11
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; CHECK-NEXT: RET64 $eax
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$eax = MOV32ri -11
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RET64 $eax
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...
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