d391e4fe84
Be more consistent in the naming convention for the various RET instructions to specify in terms of bitwidth. Helps prevent future scheduler model mismatches like those that were only addressed in D44687. Differential Revision: https://reviews.llvm.org/D113302
77 lines
1.4 KiB
YAML
77 lines
1.4 KiB
YAML
# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
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--- |
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define i32 @test_jumptable(i32 %in) {
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entry:
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switch i32 %in, label %def [
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i32 0, label %lbl1
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i32 1, label %lbl2
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i32 2, label %lbl3
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i32 3, label %lbl4
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]
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def:
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ret i32 0
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lbl1:
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ret i32 1
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lbl2:
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ret i32 2
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lbl3:
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ret i32 4
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lbl4:
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ret i32 8
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}
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...
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---
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name: test_jumptable
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jumpTable:
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kind: label-difference32
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entries:
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- id: 0
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blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
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# CHECK: [[@LINE+1]]:18: redefinition of jump table entry '%jump-table.0'
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- id: 0
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blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
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body: |
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bb.0.entry:
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successors: %bb.2.def, %bb.1.entry
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$eax = MOV32rr $edi, implicit-def $rax
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CMP32ri8 $edi, 3, implicit-def $eflags
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JCC_1 %bb.2.def, 7, implicit $eflags
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bb.1.entry:
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successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
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$rcx = LEA64r $rip, 1, _, %jump-table.0, _
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$rax = MOVSX64rm32 $rcx, 4, $rax, 0, _
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$rax = ADD64rr $rax, $rcx, implicit-def $eflags
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JMP64r $rax
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bb.2.def:
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$eax = MOV32r0 implicit-def $eflags
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RET64 $eax
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bb.3.lbl1:
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$eax = MOV32ri 1
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RET64 $eax
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bb.4.lbl2:
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$eax = MOV32ri 2
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RET64 $eax
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bb.5.lbl3:
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$eax = MOV32ri 4
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RET64 $eax
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bb.6.lbl4:
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$eax = MOV32ri 8
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RET64 $eax
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...
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