7fff1fbd3c
This hashing scheme has been useful out of tree, and I want to start experimenting with it. Specifically I want to experiment on the MIRVRegNamer, MIRCanononicalizer, and eventually the MachineOutliner. This diff is a first step, that optionally brings stable hashing to the MIRVRegNamer (and as a result, the MIRCanonicalizer). We've tested this hashing scheme on a lot of MachineOperand types that llvm::hash_value can not handle in a stable manner. This stable hashing was also the basis for "Global Machine Outliner for ThinLTO" in EuroLLVM 2020 http://llvm.org/devmtg/2020-04/talks.html#TechTalk_58 Credits: Kyungwoo Lee, Nikolai Tillmann Differential Revision: https://reviews.llvm.org/D86952
39 lines
1.7 KiB
YAML
39 lines
1.7 KiB
YAML
# RUN: llc -march=x86-64 -run-pass mir-canonicalizer -verify-machineinstrs -o - %s | FileCheck %s
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# RUN: llc -march=x86-64 -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -o - %s | FileCheck %s
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# The purpose of this test is to ensure that differing flags do in-fact cause
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# naming collisions with the new vreg renamers naming scheme.
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--- |
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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define void @baz() { unreachable }
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...
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---
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name: baz
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body: |
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bb.0:
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; CHECK: COPY
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; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = nnan VMULSSrr
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; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = ninf VMULSSrr
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; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = nsz VMULSSrr
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; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = arcp VMULSSrr
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; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = contract VMULSSrr
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; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = afn VMULSSrr
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; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = reassoc VMULSSrr
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; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = nsz arcp contract afn reassoc VMULSSrr
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; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = contract afn reassoc VMULSSrr
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%0:fr32 = COPY $xmm0
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%1:fr32 = nnan VMULSSrr %0, %0, implicit $mxcsr
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%2:fr32 = ninf VMULSSrr %1, %1, implicit $mxcsr
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%3:fr32 = nsz VMULSSrr %2, %2, implicit $mxcsr
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%4:fr32 = arcp VMULSSrr %3, %3, implicit $mxcsr
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%5:fr32 = contract VMULSSrr %4, %4, implicit $mxcsr
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%6:fr32 = afn VMULSSrr %5, %5, implicit $mxcsr
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%7:fr32 = reassoc VMULSSrr %6, %6, implicit $mxcsr
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%8:fr32 = nsz arcp contract afn reassoc VMULSSrr %7, %7, implicit $mxcsr
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%9:fr32 = contract afn reassoc VMULSSrr %8, %8, implicit $mxcsr
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$xmm0 = COPY %9
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RET 0, $xmm0
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...
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