d391e4fe84
Be more consistent in the naming convention for the various RET instructions to specify in terms of bitwidth. Helps prevent future scheduler model mismatches like those that were only addressed in D44687. Differential Revision: https://reviews.llvm.org/D113302
21 lines
733 B
YAML
21 lines
733 B
YAML
# RUN: llc -o - %s -mtriple=x86_64-- -run-pass=none | llc -o - -x mir - -mtriple=x86_64-- -run-pass=none | FileCheck %s
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---
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# CHECK-LABEL: name: func0
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# CHECK: registers:
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# CHECK: - { id: 0, class: gr32, preferred-register: '' }
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# CHECK: - { id: 1, class: gr32, preferred-register: '' }
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# CHECK: body: |
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# CHECK: bb.0:
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# CHECK: %0:gr32 = MOV32r0 implicit-def $eflags
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# CHECK: dead %1:gr32 = COPY %0
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# CHECK: MOV32mr undef $rcx, 1, $noreg, 0, $noreg, killed %0 :: (volatile store (s32))
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# CHECK: RET64 undef $eax
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name: func0
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body: |
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bb.0:
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%0 : gr32 = MOV32r0 implicit-def $eflags
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dead %1 : gr32 = COPY %0
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MOV32mr undef $rcx, 1, _, 0, _, killed %0 :: (volatile store (s32))
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RET64 undef $eax
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...
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