fae05692a3
This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
90 lines
3.1 KiB
YAML
90 lines
3.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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--- |
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@float_align1 = common global float 0.000000e+00, align 1
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@float_align4 = common global float 0.000000e+00, align 4
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@i32_align8 = common global i32 0, align 8
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define float @load_float_align1() {
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entry:
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%0 = load float, float* @float_align1, align 1
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ret float %0
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}
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define float @load_float_align4() {
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entry:
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%0 = load float, float* @float_align4, align 4
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ret float %0
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}
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define i32 @load_i32_align8() {
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entry:
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%0 = load i32, i32* @i32_align8, align 8
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ret i32 %0
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}
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...
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---
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name: load_float_align1
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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; MIPS32-LABEL: name: load_float_align1
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; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align1
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; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1
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; MIPS32: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
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; MIPS32: [[LWL:%[0-9]+]]:gpr32 = LWL [[ADDiu]], 3, [[DEF]] :: (dereferenceable load (s32) from @float_align1, align 1)
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; MIPS32: [[LWR:%[0-9]+]]:gpr32 = LWR [[ADDiu]], 0, [[LWL]] :: (dereferenceable load (s32) from @float_align1, align 1)
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; MIPS32: $f0 = COPY [[LWR]]
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; MIPS32: RetRA implicit $f0
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%1:gprb(p0) = G_GLOBAL_VALUE @float_align1
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%0:gprb(s32) = G_LOAD %1(p0) :: (dereferenceable load (s32) from @float_align1, align 1)
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$f0 = COPY %0(s32)
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RetRA implicit $f0
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...
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---
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name: load_float_align4
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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; MIPS32-LABEL: name: load_float_align4
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; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align4
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; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align4
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; MIPS32: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[ADDiu]], 0 :: (dereferenceable load (s32) from @float_align4)
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; MIPS32: $f0 = COPY [[LWC1_]]
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; MIPS32: RetRA implicit $f0
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%1:gprb(p0) = G_GLOBAL_VALUE @float_align4
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%0:fprb(s32) = G_LOAD %1(p0) :: (dereferenceable load (s32) from @float_align4)
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$f0 = COPY %0(s32)
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RetRA implicit $f0
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...
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---
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name: load_i32_align8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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; MIPS32-LABEL: name: load_i32_align8
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; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align8
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; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align8
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; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (dereferenceable load (s32) from @i32_align8, align 8)
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; MIPS32: $v0 = COPY [[LW]]
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; MIPS32: RetRA implicit $v0
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%1:gprb(p0) = G_GLOBAL_VALUE @i32_align8
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%0:gprb(s32) = G_LOAD %1(p0) :: (dereferenceable load (s32) from @i32_align8, align 8)
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$v0 = COPY %0(s32)
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RetRA implicit $v0
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...
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