fae05692a3
This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
99 lines
2.8 KiB
YAML
99 lines
2.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
|
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
|
|
--- |
|
|
|
|
define void @load1_s8_to_zextLoad1_s32(i8* %px) {entry: ret void}
|
|
define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void}
|
|
define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void}
|
|
define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void}
|
|
|
|
...
|
|
---
|
|
name: load1_s8_to_zextLoad1_s32
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.1.entry:
|
|
liveins: $a0
|
|
|
|
; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s32
|
|
; MIPS32: liveins: $a0
|
|
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
|
|
; MIPS32: [[LBu:%[0-9]+]]:gpr32 = LBu [[COPY]], 0 :: (load (s8) from %ir.px)
|
|
; MIPS32: $v0 = COPY [[LBu]]
|
|
; MIPS32: RetRA implicit $v0
|
|
%0:gprb(p0) = COPY $a0
|
|
%2:gprb(s32) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)
|
|
$v0 = COPY %2(s32)
|
|
RetRA implicit $v0
|
|
|
|
...
|
|
---
|
|
name: load2_s16_to_zextLoad2_s32
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.1.entry:
|
|
liveins: $a0
|
|
|
|
; MIPS32-LABEL: name: load2_s16_to_zextLoad2_s32
|
|
; MIPS32: liveins: $a0
|
|
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
|
|
; MIPS32: [[LHu:%[0-9]+]]:gpr32 = LHu [[COPY]], 0 :: (load (s16) from %ir.px)
|
|
; MIPS32: $v0 = COPY [[LHu]]
|
|
; MIPS32: RetRA implicit $v0
|
|
%0:gprb(p0) = COPY $a0
|
|
%2:gprb(s32) = G_ZEXTLOAD %0(p0) :: (load (s16) from %ir.px)
|
|
$v0 = COPY %2(s32)
|
|
RetRA implicit $v0
|
|
|
|
...
|
|
---
|
|
name: load1_s8_to_sextLoad1_s32
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.1.entry:
|
|
liveins: $a0
|
|
|
|
; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s32
|
|
; MIPS32: liveins: $a0
|
|
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
|
|
; MIPS32: [[LB:%[0-9]+]]:gpr32 = LB [[COPY]], 0 :: (load (s8) from %ir.px)
|
|
; MIPS32: $v0 = COPY [[LB]]
|
|
; MIPS32: RetRA implicit $v0
|
|
%0:gprb(p0) = COPY $a0
|
|
%2:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)
|
|
$v0 = COPY %2(s32)
|
|
RetRA implicit $v0
|
|
|
|
...
|
|
---
|
|
name: load2_s16_to_sextLoad2_s32
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.1.entry:
|
|
liveins: $a0
|
|
|
|
; MIPS32-LABEL: name: load2_s16_to_sextLoad2_s32
|
|
; MIPS32: liveins: $a0
|
|
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
|
|
; MIPS32: [[LH:%[0-9]+]]:gpr32 = LH [[COPY]], 0 :: (load (s16) from %ir.px)
|
|
; MIPS32: $v0 = COPY [[LH]]
|
|
; MIPS32: RetRA implicit $v0
|
|
%0:gprb(p0) = COPY $a0
|
|
%2:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s16) from %ir.px)
|
|
$v0 = COPY %2(s32)
|
|
RetRA implicit $v0
|
|
|
|
...
|