623282f0dd
Support for 64-bit coprocessors on a 32-bit architecture was added in `MIPS32 R2`. llvm-svn: 365507
83 lines
3.1 KiB
LLVM
83 lines
3.1 KiB
LLVM
; Test the MSA floating point conversion intrinsics (e.g. float->double) that
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; are encoded with the 2RF instruction format.
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; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
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; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
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@llvm_mips_fexupl_w_ARG1 = global <8 x half> <half 0.000000e+00, half 1.000000e+00, half 2.000000e+00, half 3.000000e+00, half 4.000000e+00, half 5.000000e+00, half 6.000000e+00, half 7.000000e+00>, align 16
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@llvm_mips_fexupl_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
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define void @llvm_mips_fexupl_w_test() nounwind {
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entry:
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%0 = load <8 x half>, <8 x half>* @llvm_mips_fexupl_w_ARG1
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%1 = tail call <4 x float> @llvm.mips.fexupl.w(<8 x half> %0)
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store <4 x float> %1, <4 x float>* @llvm_mips_fexupl_w_RES
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ret void
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}
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declare <4 x float> @llvm.mips.fexupl.w(<8 x half>) nounwind
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; CHECK: llvm_mips_fexupl_w_test:
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; CHECK: ld.h
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; CHECK: fexupl.w
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; CHECK: st.w
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; CHECK: .size llvm_mips_fexupl_w_test
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;
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@llvm_mips_fexupl_d_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
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@llvm_mips_fexupl_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
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define void @llvm_mips_fexupl_d_test() nounwind {
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entry:
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%0 = load <4 x float>, <4 x float>* @llvm_mips_fexupl_d_ARG1
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%1 = tail call <2 x double> @llvm.mips.fexupl.d(<4 x float> %0)
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store <2 x double> %1, <2 x double>* @llvm_mips_fexupl_d_RES
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ret void
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}
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declare <2 x double> @llvm.mips.fexupl.d(<4 x float>) nounwind
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; CHECK: llvm_mips_fexupl_d_test:
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; CHECK: ld.w
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; CHECK: fexupl.d
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; CHECK: st.d
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; CHECK: .size llvm_mips_fexupl_d_test
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;
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@llvm_mips_fexupr_w_ARG1 = global <8 x half> <half 0.000000e+00, half 1.000000e+00, half 2.000000e+00, half 3.000000e+00, half 4.000000e+00, half 5.000000e+00, half 6.000000e+00, half 7.000000e+00>, align 16
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@llvm_mips_fexupr_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
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define void @llvm_mips_fexupr_w_test() nounwind {
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entry:
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%0 = load <8 x half>, <8 x half>* @llvm_mips_fexupr_w_ARG1
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%1 = tail call <4 x float> @llvm.mips.fexupr.w(<8 x half> %0)
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store <4 x float> %1, <4 x float>* @llvm_mips_fexupr_w_RES
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ret void
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}
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declare <4 x float> @llvm.mips.fexupr.w(<8 x half>) nounwind
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; CHECK: llvm_mips_fexupr_w_test:
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; CHECK: ld.h
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; CHECK: fexupr.w
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; CHECK: st.w
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; CHECK: .size llvm_mips_fexupr_w_test
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;
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@llvm_mips_fexupr_d_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
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@llvm_mips_fexupr_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
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define void @llvm_mips_fexupr_d_test() nounwind {
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entry:
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%0 = load <4 x float>, <4 x float>* @llvm_mips_fexupr_d_ARG1
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%1 = tail call <2 x double> @llvm.mips.fexupr.d(<4 x float> %0)
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store <2 x double> %1, <2 x double>* @llvm_mips_fexupr_d_RES
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ret void
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}
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declare <2 x double> @llvm.mips.fexupr.d(<4 x float>) nounwind
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; CHECK: llvm_mips_fexupr_d_test:
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; CHECK: ld.w
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; CHECK: fexupr.d
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; CHECK: st.d
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; CHECK: .size llvm_mips_fexupr_d_test
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;
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