719bac55df
When parsing MachineMemOperands, MIRParser treated the "align" keyword
the same as "basealign". Really "basealign" should specify the
alignment of the MachinePointerInfo base value, and "align" should
specify the alignment of that base value plus the offset.
This worked OK when the specified alignment was no larger than the
alignment of the offset, but in cases like this it just caused
confusion:
STW killed %18, 4, %stack.1.ap2.i.i :: (store (s32) into %stack.1.ap2.i.i + 4, align 8)
MIRPrinter would never have printed this, with an offset of 4 but an
align of 8, so it must have been written by hand. MIRParser would
interpret "align 8" as "basealign 8", but I think it is better to give
an error and force the user to write "basealign 8" if that is what they
really meant.
Differential Revision: https://reviews.llvm.org/D120400
Change-Id: I7eeeefc55c2df3554ba8d89f8809a2f45ada32d8
222 lines
11 KiB
YAML
222 lines
11 KiB
YAML
# RUN: llc %s -start-after=shrink-wrap -march=mips64 -mcpu=mips64r6 -mattr=+fp64,+msa -o /dev/null
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# Test that estimated size of the stack leads to the creation of an emergency
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# spill when MSA is in use. Previously, this test case would fail during
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# register scavenging due to the lack of a spill slot.
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--- |
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define inreg { i64, i64 } @test(i64 inreg %a.coerce0, i64 inreg %a.coerce1, i64 inreg %b.coerce0, i64 inreg %b.coerce1, i32 signext %c) #0 {
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entry:
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%retval = alloca <16 x i8>, align 16
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%a = alloca <16 x i8>, align 16
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%b = alloca <16 x i8>, align 16
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%a.addr = alloca <16 x i8>, align 16
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%b.addr = alloca <16 x i8>, align 16
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%c.addr = alloca i32, align 4
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%g = alloca <16 x i8>*, align 8
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%d = alloca i8*, align 8
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%0 = bitcast <16 x i8>* %a to { i64, i64 }*
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%1 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %0, i32 0, i32 0
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store i64 %a.coerce0, i64* %1, align 16
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%2 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %0, i32 0, i32 1
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store i64 %a.coerce1, i64* %2, align 8
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%a1 = load <16 x i8>, <16 x i8>* %a, align 16
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%3 = bitcast <16 x i8>* %b to { i64, i64 }*
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%4 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %3, i32 0, i32 0
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store i64 %b.coerce0, i64* %4, align 16
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%5 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %3, i32 0, i32 1
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store i64 %b.coerce1, i64* %5, align 8
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%b2 = load <16 x i8>, <16 x i8>* %b, align 16
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store <16 x i8> %a1, <16 x i8>* %a.addr, align 16
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store <16 x i8> %b2, <16 x i8>* %b.addr, align 16
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store i32 %c, i32* %c.addr, align 4
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%6 = alloca i8, i64 6400, align 16
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%7 = bitcast i8* %6 to <16 x i8>*
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store <16 x i8>* %7, <16 x i8>** %g, align 8
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%8 = load <16 x i8>*, <16 x i8>** %g, align 8
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call void @h(<16 x i8>* %b.addr, <16 x i8>* %8)
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%9 = load <16 x i8>*, <16 x i8>** %g, align 8
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%10 = bitcast <16 x i8>* %9 to i8*
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store i8* %10, i8** %d, align 8
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%11 = load <16 x i8>, <16 x i8>* %a.addr, align 16
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%12 = load i8*, i8** %d, align 8
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%arrayidx = getelementptr inbounds i8, i8* %12, i64 0
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%13 = load i8, i8* %arrayidx, align 1
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%conv = sext i8 %13 to i32
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%14 = call <16 x i8> @llvm.mips.fill.b(i32 %conv)
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%add = add <16 x i8> %11, %14
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%15 = load i8*, i8** %d, align 8
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%arrayidx3 = getelementptr inbounds i8, i8* %15, i64 1
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%16 = load i8, i8* %arrayidx3, align 1
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%conv4 = sext i8 %16 to i32
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%17 = call <16 x i8> @llvm.mips.fill.b(i32 %conv4)
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%add5 = add <16 x i8> %add, %17
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%18 = load <16 x i8>, <16 x i8>* %b.addr, align 16
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%add6 = add <16 x i8> %18, %add5
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store <16 x i8> %add6, <16 x i8>* %b.addr, align 16
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%19 = load <16 x i8>, <16 x i8>* %b.addr, align 16
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store <16 x i8> %19, <16 x i8>* %retval, align 16
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%20 = bitcast <16 x i8>* %retval to { i64, i64 }*
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%21 = load { i64, i64 }, { i64, i64 }* %20, align 16
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ret { i64, i64 } %21
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}
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declare void @h(<16 x i8>*, <16 x i8>*)
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declare <16 x i8> @llvm.mips.fill.b(i32)
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declare void @llvm.stackprotector(i8*, i8**)
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...
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---
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name: test
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alignment: 8
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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liveins:
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- { reg: '$a0_64', virtual-reg: '' }
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- { reg: '$a1_64', virtual-reg: '' }
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- { reg: '$a2_64', virtual-reg: '' }
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- { reg: '$a3_64', virtual-reg: '' }
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- { reg: '$t0_64', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 16
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adjustsStack: false
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hasCalls: true
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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- { id: 0, name: retval, type: default, offset: 0, size: 16, alignment: 16,
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callee-saved-register: '', debug-info-variable: '',
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debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: a, type: default, offset: 0, size: 16, alignment: 16,
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callee-saved-register: '', debug-info-variable: '',
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debug-info-expression: '', debug-info-location: '' }
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- { id: 2, name: b, type: default, offset: 0, size: 16, alignment: 16,
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callee-saved-register: '', debug-info-variable: '',
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debug-info-expression: '', debug-info-location: '' }
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- { id: 3, name: a.addr, type: default, offset: 0, size: 16, alignment: 16,
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callee-saved-register: '', debug-info-variable: '',
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debug-info-expression: '', debug-info-location: '' }
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- { id: 4, name: b.addr, type: default, offset: 0, size: 16, alignment: 16,
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callee-saved-register: '', debug-info-variable: '',
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debug-info-expression: '', debug-info-location: '' }
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- { id: 5, name: c.addr, type: default, offset: 0, size: 4, alignment: 4,
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callee-saved-register: '', debug-info-variable: '',
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debug-info-expression: '', debug-info-location: '' }
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- { id: 6, name: g, type: default, offset: 0, size: 8, alignment: 8,
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callee-saved-register: '', debug-info-variable: '',
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debug-info-expression: '', debug-info-location: '' }
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- { id: 7, name: d, type: default, offset: 0, size: 8, alignment: 8,
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callee-saved-register: '', debug-info-variable: '',
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debug-info-expression: '', debug-info-location: '' }
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- { id: 8, name: '', type: default, offset: 0, size: 6400,
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alignment: 16, callee-saved-register: '', debug-info-variable: '',
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debug-info-expression: '', debug-info-location: '' }
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constants:
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body: |
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bb.0.entry:
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liveins: $a0_64, $a1_64, $a2_64, $a3_64, $t0_64
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SD killed $a0_64, %stack.1.a, 0 :: (store (s64) into %ir.1, align 16)
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SD killed $a1_64, %stack.1.a, 8 :: (store (s64) into %ir.2)
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$w0 = LD_B %stack.1.a, 0 :: (dereferenceable load (s128) from %ir.a)
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SD killed $a2_64, %stack.2.b, 0 :: (store (s64) into %ir.4, align 16)
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SD killed $a3_64, %stack.2.b, 8 :: (store (s64) into %ir.5)
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$w1 = LD_B %stack.2.b, 0 :: (dereferenceable load (s128) from %ir.b)
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ST_B killed $w0, %stack.3.a.addr, 0 :: (store (s128) into %ir.a.addr)
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ST_B killed $w1, %stack.4.b.addr, 0 :: (store (s128) into %ir.b.addr)
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SW $t0, %stack.5.c.addr, 0, implicit killed $t0_64 :: (store (s32) into %ir.c.addr)
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$at_64 = LEA_ADDiu64 %stack.8, 0
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SD killed $at_64, %stack.6.g, 0 :: (store (s64) into %ir.g)
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$a1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
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$a0_64 = LEA_ADDiu64 %stack.4.b.addr, 0
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JAL @h, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $a1_64, implicit-def $sp
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ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
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$at_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$v0_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$v1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$a0_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$a1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$a2_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$a3_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$t0_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$t1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$t2_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$t3_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$t4_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$t5_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$t6_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$t7_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$s0_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$s1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$s2_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$s3_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$s4_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$s5_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$s6_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$s7_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$t8_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$t9_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$ra_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
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$w0 = LD_B %stack.3.a.addr, 0 :: (dereferenceable load (s128) from %ir.a.addr)
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SD $at_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $v0_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $v1_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $a0_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $a1_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $a2_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $a3_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $t0_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $t1_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $t2_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $t3_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $t4_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $t5_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $t6_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $t7_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $s0_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $s1_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $s2_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $s3_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $s4_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $s5_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $s6_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $s7_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $t8_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $t9_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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SD $ra_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
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$at_64 = LD %stack.7.d, 0 :: (dereferenceable load (s64) from %ir.d)
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$v0 = LB $at_64, 0 :: (load (s8) from %ir.arrayidx)
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$w1 = FILL_B killed $v0
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$w0 = ADDV_B killed $w0, killed $w1
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$at = LB killed $at_64, 1 :: (load (s8) from %ir.arrayidx3)
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$w1 = FILL_B killed $at
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$w0 = ADDV_B killed $w0, killed $w1
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$w1 = LD_B %stack.4.b.addr, 0 :: (dereferenceable load (s128) from %ir.b.addr)
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$w0 = ADDV_B killed $w1, killed $w0
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ST_B killed $w0, %stack.4.b.addr, 0 :: (store (s128) into %ir.b.addr)
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$w0 = LD_B %stack.4.b.addr, 0 :: (dereferenceable load (s128) from %ir.b.addr)
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ST_B killed $w0, %stack.0.retval, 0 :: (store (s128) into %ir.retval)
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$v0_64 = LD %stack.0.retval, 0 :: (dereferenceable load (s64) from %ir.20, basealign 16)
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$v1_64 = LD %stack.0.retval, 8 :: (dereferenceable load (s64) from %ir.20 + 8, basealign 16)
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RetRA implicit $v0_64, implicit $v1_64
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...
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