bef3eb8344
Adds NVPTX intrinsics and builtins for CUDA PTX cvt instructions for sm80 architectures and above. Requires ptx 7.0. PTX ISA description of cvt instructions : https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cvt Signed-off-by: JackAKirk <jack.kirk@codeplay.com> Differential Revision: https://reviews.llvm.org/D116673
137 lines
3.2 KiB
LLVM
137 lines
3.2 KiB
LLVM
; RUN: llc < %s -march=nvptx64 -mcpu=sm_80 -mattr=+ptx70 | FileCheck %s
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; CHECK-LABEL: cvt_rn_bf16x2_f32
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define i32 @cvt_rn_bf16x2_f32(float %f1, float %f2) {
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; CHECK: cvt.rn.bf16x2.f32
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%val = call i32 @llvm.nvvm.ff2bf16x2.rn(float %f1, float %f2);
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ret i32 %val
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}
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; CHECK-LABEL: cvt_rn_relu_bf16x2_f32
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define i32 @cvt_rn_relu_bf16x2_f32(float %f1, float %f2) {
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; CHECK: cvt.rn.relu.bf16x2.f32
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%val = call i32 @llvm.nvvm.ff2bf16x2.rn.relu(float %f1, float %f2);
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ret i32 %val
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}
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; CHECK-LABEL: cvt_rz_bf16x2_f32
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define i32 @cvt_rz_bf16x2_f32(float %f1, float %f2) {
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; CHECK: cvt.rz.bf16x2.f32
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%val = call i32 @llvm.nvvm.ff2bf16x2.rz(float %f1, float %f2);
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ret i32 %val
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}
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; CHECK-LABEL: cvt_rz_relu_bf16x2_f32
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define i32 @cvt_rz_relu_bf16x2_f32(float %f1, float %f2) {
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; CHECK: cvt.rz.relu.bf16x2.f32
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%val = call i32 @llvm.nvvm.ff2bf16x2.rz.relu(float %f1, float %f2);
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ret i32 %val
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}
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declare i32 @llvm.nvvm.ff2bf16x2.rn(float, float)
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declare i32 @llvm.nvvm.ff2bf16x2.rn.relu(float, float)
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declare i32 @llvm.nvvm.ff2bf16x2.rz(float, float)
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declare i32 @llvm.nvvm.ff2bf16x2.rz.relu(float, float)
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; CHECK-LABEL: cvt_rn_f16x2_f32
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define <2 x half> @cvt_rn_f16x2_f32(float %f1, float %f2) {
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; CHECK: cvt.rn.f16x2.f32
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%val = call <2 x half> @llvm.nvvm.ff2f16x2.rn(float %f1, float %f2);
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ret <2 x half> %val
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}
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; CHECK-LABEL: cvt_rn_relu_f16x2_f32
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define <2 x half> @cvt_rn_relu_f16x2_f32(float %f1, float %f2) {
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; CHECK: cvt.rn.relu.f16x2.f32
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%val = call <2 x half> @llvm.nvvm.ff2f16x2.rn.relu(float %f1, float %f2);
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ret <2 x half> %val
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}
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; CHECK-LABEL: cvt_rz_f16x2_f32
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define <2 x half> @cvt_rz_f16x2_f32(float %f1, float %f2) {
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; CHECK: cvt.rz.f16x2.f32
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%val = call <2 x half> @llvm.nvvm.ff2f16x2.rz(float %f1, float %f2);
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ret <2 x half> %val
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}
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; CHECK-LABEL: cvt_rz_relu_f16x2_f32
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define <2 x half> @cvt_rz_relu_f16x2_f32(float %f1, float %f2) {
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; CHECK: cvt.rz.relu.f16x2.f32
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%val = call <2 x half> @llvm.nvvm.ff2f16x2.rz.relu(float %f1, float %f2);
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ret <2 x half> %val
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}
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declare <2 x half> @llvm.nvvm.ff2f16x2.rn(float, float)
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declare <2 x half> @llvm.nvvm.ff2f16x2.rn.relu(float, float)
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declare <2 x half> @llvm.nvvm.ff2f16x2.rz(float, float)
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declare <2 x half> @llvm.nvvm.ff2f16x2.rz.relu(float, float)
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; CHECK-LABEL: cvt_rn_bf16_f32
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define i16 @cvt_rn_bf16_f32(float %f1) {
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; CHECK: cvt.rn.bf16.f32
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%val = call i16 @llvm.nvvm.f2bf16.rn(float %f1);
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ret i16 %val
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}
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; CHECK-LABEL: cvt_rn_relu_bf16_f32
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define i16 @cvt_rn_relu_bf16_f32(float %f1) {
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; CHECK: cvt.rn.relu.bf16.f32
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%val = call i16 @llvm.nvvm.f2bf16.rn.relu(float %f1);
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ret i16 %val
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}
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; CHECK-LABEL: cvt_rz_bf16_f32
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define i16 @cvt_rz_bf16_f32(float %f1) {
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; CHECK: cvt.rz.bf16.f32
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%val = call i16 @llvm.nvvm.f2bf16.rz(float %f1);
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ret i16 %val
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}
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; CHECK-LABEL: cvt_rz_relu_bf16_f32
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define i16 @cvt_rz_relu_bf16_f32(float %f1) {
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; CHECK: cvt.rz.relu.bf16.f32
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%val = call i16 @llvm.nvvm.f2bf16.rz.relu(float %f1);
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ret i16 %val
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}
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declare i16 @llvm.nvvm.f2bf16.rn(float)
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declare i16 @llvm.nvvm.f2bf16.rn.relu(float)
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declare i16 @llvm.nvvm.f2bf16.rz(float)
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declare i16 @llvm.nvvm.f2bf16.rz.relu(float)
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; CHECK-LABEL: cvt_rna_tf32_f32
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define i32 @cvt_rna_tf32_f32(float %f1) {
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; CHECK: cvt.rna.tf32.f32
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%val = call i32 @llvm.nvvm.f2tf32.rna(float %f1);
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ret i32 %val
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}
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declare i32 @llvm.nvvm.f2tf32.rna(float)
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