ba627a32e1
This patch includes the following updates to the load/store refactoring effort introduced in D93370: - Update various VSX patterns that use to "force" an XForm, to instead just XForm. This allows the ability for the patterns to compute the most optimal addressing mode (and to produce a DForm instruction when possible) - Update pattern and test case for the LXVD2X/STXVD2X intrinsics - Update LIT test cases that use to use the XForm instruction to use the DForm instruction Differential Revision: https://reviews.llvm.org/D95115
148 lines
4.0 KiB
LLVM
148 lines
4.0 KiB
LLVM
; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s
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; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr9 -mattr=-direct-move | FileCheck %s -check-prefix=CHECK-P9
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@d = common global double 0.000000e+00, align 8
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@f = common global float 0.000000e+00, align 4
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@i = common global i32 0, align 4
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@ui = common global i32 0, align 4
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; Function Attrs: nounwind
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define void @dblToInt() #0 {
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entry:
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%ii = alloca i32, align 4
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%0 = load double, double* @d, align 8
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%conv = fptosi double %0 to i32
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store volatile i32 %conv, i32* %ii, align 4
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ret void
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; CHECK-LABEL: @dblToInt
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; CHECK: xscvdpsxws [[REGCONV1:[0-9]+]],
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; CHECK: stfiwx [[REGCONV1]],
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}
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; Function Attrs: nounwind
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define void @fltToInt() #0 {
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entry:
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%ii = alloca i32, align 4
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%0 = load float, float* @f, align 4
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%conv = fptosi float %0 to i32
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store volatile i32 %conv, i32* %ii, align 4
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ret void
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; CHECK-LABEL: @fltToInt
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; CHECK: xscvdpsxws [[REGCONV2:[0-9]+]],
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; CHECK: stfiwx [[REGCONV2]],
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}
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; Function Attrs: nounwind
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define void @intToDbl() #0 {
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entry:
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%dd = alloca double, align 8
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%0 = load i32, i32* @i, align 4
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%conv = sitofp i32 %0 to double
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store volatile double %conv, double* %dd, align 8
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ret void
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; CHECK-LABEL: @intToDbl
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; CHECK: lfiwax [[REGLD1:[0-9]+]],
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; CHECK: xscvsxddp {{[0-9]+}}, [[REGLD1]]
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}
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; Function Attrs: nounwind
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define void @intToFlt() #0 {
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entry:
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%ff = alloca float, align 4
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%0 = load i32, i32* @i, align 4
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%conv = sitofp i32 %0 to float
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store volatile float %conv, float* %ff, align 4
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ret void
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; CHECK-LABEL: @intToFlt
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; CHECK: lfiwax [[REGLD2:[0-9]+]],
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; CHECK: xscvsxdsp {{[0-9]}}, [[REGLD2]]
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}
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; Function Attrs: nounwind
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define void @dblToUInt() #0 {
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entry:
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%uiui = alloca i32, align 4
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%0 = load double, double* @d, align 8
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%conv = fptoui double %0 to i32
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store volatile i32 %conv, i32* %uiui, align 4
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ret void
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; CHECK-LABEL: @dblToUInt
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; CHECK: xscvdpuxws [[REGCONV3:[0-9]+]],
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; CHECK: stfiwx [[REGCONV3]],
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}
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; Function Attrs: nounwind
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define void @fltToUInt() #0 {
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entry:
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%uiui = alloca i32, align 4
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%0 = load float, float* @f, align 4
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%conv = fptoui float %0 to i32
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store volatile i32 %conv, i32* %uiui, align 4
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ret void
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; CHECK-LABEL: @fltToUInt
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; CHECK: xscvdpuxws [[REGCONV4:[0-9]+]],
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; CHECK: stfiwx [[REGCONV4]],
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}
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; Function Attrs: nounwind
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define void @uIntToDbl() #0 {
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entry:
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%dd = alloca double, align 8
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%0 = load i32, i32* @ui, align 4
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%conv = uitofp i32 %0 to double
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store volatile double %conv, double* %dd, align 8
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ret void
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; CHECK-LABEL: @uIntToDbl
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; CHECK: lfiwzx [[REGLD3:[0-9]+]],
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; CHECK: xscvuxddp {{[0-9]+}}, [[REGLD3]]
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}
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; Function Attrs: nounwind
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define void @uIntToFlt() #0 {
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entry:
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%ff = alloca float, align 4
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%0 = load i32, i32* @ui, align 4
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%conv = uitofp i32 %0 to float
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store volatile float %conv, float* %ff, align 4
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ret void
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; CHECK-LABEL: @uIntToFlt
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; CHECK: lfiwzx [[REGLD4:[0-9]+]],
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; CHECK: xscvuxdsp {{[0-9]+}}, [[REGLD4]]
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}
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; Function Attrs: nounwind
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define void @dblToFloat() #0 {
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entry:
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%ff = alloca float, align 4
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%0 = load double, double* @d, align 8
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%conv = fptrunc double %0 to float
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store volatile float %conv, float* %ff, align 4
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ret void
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; CHECK-LABEL: @dblToFloat
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; CHECK: lfd [[REGLD5:[0-9]+]],
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; CHECK: stfs [[REGLD5]],
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; CHECK-P9-LABEL: @dblToFloat
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; CHECK-P9: lfd [[REGLD5:[0-9]+]],
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; CHECK-P9: stfs [[REGLD5]],
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}
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; Function Attrs: nounwind
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define void @floatToDbl() #0 {
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entry:
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%dd = alloca double, align 8
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%0 = load float, float* @f, align 4
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%conv = fpext float %0 to double
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store volatile double %conv, double* %dd, align 8
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ret void
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; CHECK-LABEL: @floatToDbl
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; CHECK: lfs [[REGLD5:[0-9]+]],
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; CHECK: stfd [[REGLD5]],
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; CHECK-P9-LABEL: @floatToDbl
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; CHECK-P9: lfs [[REGLD5:[0-9]+]],
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; CHECK-P9: stfd [[REGLD5]],
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}
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